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| Patent # | Description |
|---|---|
| US-5,537,583 |
Method and apparatus for a fault tolerant clock with dynamic
reconfiguration A fail-operational/fail-operational fault tolerant clock includes a voting core comprised of triple redundant clock modules (30, 40, 50) and a floating hot spare... |
| US-5,537,582 |
Bus interface circuitry for synchronizing central processors running at
multiple clock frequencies to other... A central processing unit including apparatus for controlling transfer of data and addresses to and from the central processing unit including circuitry for... |
| US-5,537,581 |
Microprocessor with a core that operates at multiple frequencies A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a... |
| US-5,537,580 |
Integrated circuit fabrication using state machine extraction from
behavioral hardware description language A method for fabricating an integrated circuit includes the steps of: (a) describing the functionality of an integrated circuit in terms of a behavioral hardware... |
| US-5,537,579 |
Method and apparatus for managing color data A method and apparatus for managing color data in a predetermined color space by using a pallet converting mechanism, in which a pallet management table can be... |
| US-5,537,578 |
Transparent driving partition for processing logical volumes to be
recorded onto optical media A system for recording on a rewritable (erasable) optical disk is provided which reduces the data integrity exposure and negative performance impact of separate... |
| US-5,537,577 |
Interleaved memory wherein plural memory means comprising plural banks
output data simultaneously while a... An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the... |
| US-5,537,576 |
Expandable memory for a digital signal processor including mapped first
and second memory banks forming a... A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single... |
| US-5,537,575 |
System for handling cache memory victim data which transfers data from
cache to the interface while CPU... A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having... |
| US-5,537,574 |
Sysplex shared data coherency method A method for controlling coherence of data elements sharable among a plurality of independently-operating CPCs (central processing complexes) in a multi-system... |
| US-5,537,573 |
Cache system and method for prefetching of data A cache system which includes prefetch pointer fields for identifying lines of memory to prefetch thereby minimizing the occurrence of cache misses. This cache... |
| US-5,537,572 |
Cache controller and method for dumping contents of a cache directory
and cache data random access memory (RAM) A cache memory controller and method for dumping the contents of a cache directory and a cache data random access memory (RAM) are described. In order to dump... |
| US-5,537,571 |
Control device for a buffer memory with reconfigurable partitioning Control device for a buffer memory which distinguishes information of the "instruction" type and information of the "data" type, and which replaces stored... |
| US-5,537,570 |
Cache with a tag duplicate fault avoidance system and method A method for avoiding a tag duplicate fault. The method includes the steps of using a master - slave tag; selecting a first tag as a master and a second tag as a... |
| US-5,537,569 |
Multiprocessor system utilizing a directory memory and including grouped
processing elements each having cache In a shared memory type multiprocessing system, when data stored in each processing element is managed in a directory method, a plurality of processing elements... |
| US-5,537,568 |
System for dynamically controlling cache manager maintaining cache index
and controlling sequential data access A cache management system and method monitors and controls the contents of cache memory coupled to at least one host and at least one data storage device. A... |
| US-5,537,567 |
Parity block configuration in an array of storage devices In a redundant array of disk storage units which independently accesses data blocks on different units and which uses parity blocks for data protection, parity... |
| US-5,537,566 |
Apparatus and method for controlling background processing in disk array
device An apparatus and method for controlling a background process in a disk array device including a disk array control unit which accesses the plurality of storage... |
| US-5,537,565 |
Dynamic memory system having memory refresh An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh... |
| US-5,537,564 |
Technique for accessing and refreshing memory locations within
electronic storage devices which need to be... A technique for accessing and refreshing memory locations within a plurality of electronic storage devices which need to be refreshed is disclosed. The technique... |
| US-5,537,563 |
Devices, systems and methods for accessing data using a gun preferred
data organization A processing system operates on data words each having first and second portions. A first memory stores the first portion of a first data word accessible by a... |
| US-5,537,562 |
Data processing system and method thereof A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations... |
| US-5,537,561 |
Processor A processor with a plurality of operational pipelines for performing parallel processing which is includes an instruction processing section with a plurality of... |
| US-5,537,560 |
Method and apparatus for conditionally generating a microinstruction
that selects one of two values based upon... The present invention provides a microinstruction for conditionally selecting one of two data values based upon control states of a processor. The... |
| US-5,537,559 |
Exception handling circuit and method A microprocessor circuit monitors addresses generated by the microprocessor to check for various address-exception conditions. Fetch-exception status bits are... |
| US-5,537,558 |
Apparatus and method for communicating multiple devices through one
PCMCIA interface An apparatus that connects to a standard PCMCIA interface of a microprocessor-based computer which typically communicates with only a single external device... |
| US-5,537,557 |
Interface between unsynchronised devices An interface between unsynchronised devices such as ASICs. The interface comprises a delay means which synchronises the write strobe of the first device with the... |
| US-5,537,556 |
System and method for interfacing a CPU to a video controller Interfacing a video subsystem capable of driving a video display monitor to a personal computer (PC) architecture. The system and method involves connecting the... |
| US-5,537,555 |
Fully pipelined and highly concurrent memory controller A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize... |
| US-5,537,554 |
Method and apparatus for controlling and communicating with business
office devices A method and apparatus for controlling and communicating with business office devices, such as copiers, facsimiles and/or printers. The present invention... |
| US-5,537,553 |
Method of and apparatus for bus control and data processor In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a... |
| US-5,537,552 |
Apparatus for selectively comparing pointers to detect full or empty
status of a circular buffer area in an... An information reproducing apparatus for reproducing recorded data includes a buffer, a control device and a determining device. The buffer stores data blocks... |
| US-5,537,551 |
Data compression method for use in a computerized informational and
transactional network A method for compressing and subsequently decompressing digital data communicated in an interactive computer network, the network designed to provide... |
| US-5,537,550 |
Interactive network board for logging peripheral statistics with logging
level commands Method and apparatus for logging status information of a printer using an interactive network board coupled between the printer and a Local Area Network,... |
| US-5,537,549 |
Communication network with time coordinated station activity by time
slot and periodic interval number Activity on a digital communication network is divided into periodic intervals and during a segment of each periodic interval a moderator station broadcasts a... |
| US-5,537,548 |
Method of computer conferencing by intercepting commands issued by
application programs and redirecting to all... During execution, API calls to the operating system in a master processor are transferred to slave processors by an event redirection mechanism, the API calls... |
| US-5,537,547 |
Automatic network element identity information distribution apparatus
and method In a telecommunications management network including a network element provisioned as a so-called Directory Services Network Element (DSNE) and at least one... |
| US-5,537,546 |
High-level adaptable bidirectional protocol for use between a hypermedia
system and a plurality of editors A very high-level bidirectional protocol (CP) used for communication between a hypermedia system (HS) and a large number of interconnected editors (HSE, Ea, Eb,... |
| US-5,537,545 |
System for controlling cooperations among a plurality of terminals
connected to a network whereby each terminal... Each of a plurality of terminals includes a processing section, a cooperation controlling section and an inputting section. The inputting section inputs, to the... |
| US-5,537,544 |
Portable computer system having password control means for holding one
or more passwords such that the... A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data... |
| US-5,537,543 |
Electronic mail drive type computer system and file operation method
having a mail terminal operating... In an arrangement of a mail terminal 1, an electronic mail system 2, a job control terminal 4, and a computer system 3, a user makes a proposal of a file... |
| US-5,537,542 |
Apparatus and method for managing a server workload according to client
performance goals in a client/server... A workload manager creates an in storage representation of a set of performance goals, each goal associated with a class of clients (e.g., client transactions)... |
| US-5,537,541 |
System independent interface for performance counters In a computer system, events indicative of the performance of the system are generated by system hardware and software. A user requests control of counters of... |
| US-5,537,540 |
Transparent, secure computer virus detection method and apparatus A computer system which verifies the integrity of installed software on the computer system. A reserved non-DOS hard disk partition is used to store routines... |
| US-5,537,539 |
Method and apparatus for controlling a computer system A method and apparatus for controlling a computer system having an operating system program, that constitutes a given operating system and that carries out... |
| US-5,537,538 |
Debug mode for a superscalar RISC processor A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise... |
| US-5,537,537 |
Burn-in diagnostic technique for a disc driving apparatus A hard disc drive includes a self-diagnostic program which is stored either in ROM, on the magnetic disc or the like. This program enables the disc drive to be... |
| US-5,537,536 |
Apparatus and method for debugging electronic components through an
in-circuit emulator A circuit controlling the transmission of information from a testing probe to an ICE.TM. base unit for debugging an electronic component having a dedicated bus.... |
| US-5,537,535 |
Multi-CPU system having fault monitoring facility A multi-CPU system including a fault monitoring facility comprises a plurality of central processing units interconnected through a system bus and sending and... |
| US-5,537,534 |
Disk array having redundant storage and methods for incrementally
generating redundancy as data is written to... A data storage system has a disk array having multiple storage disks and a disk array controller coupled to the disk array to coordinate data transfer to and... |
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