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| Patent # | Description |
|---|---|
| US-5,568,655 |
Detection of pager signal in FM radio transmission Apparatus for detecting the presence of a paging signal at 57 KHz in a frequency modulated transmission includes a phase locked loop (14) which is sensitive to... |
| US-5,568,654 |
Mobile radio telecommunications system In a mobile radio telecommunications system having a switching unit, a control station connected to the switching unit, a plurality of base stations connected to... |
| US-5,568,653 |
Method of producing a sintered carbonitride alloy for semifinishing
machining According to the invention there now is provided a method of producing a sintered titanium based carbonitride alloy with 3-25 weight-% binder phase with... |
| US-5,568,652 |
Rapid setting compositions and method of making and using same A method of making a homogeneous formable mixture involves simultaneously mixing organic binder which can be cellulose ethers, cellulose ether derivatives, and... |
| US-5,568,651 |
Method for detection of configuration types and addressing modes of a
dynamic RAM A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM... |
| US-5,568,650 |
Control unit for controlling reading and writing of a magnetic tape unit The control unit for the magnetic tape unit compresses data and writes in a physical block unit in the buffer according to the data write instruction from the... |
| US-5,568,649 |
Interrupt cascading and priority configuration for a symmetrical
multiprocessing system A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of... |
| US-5,568,648 |
Indirect addressing of channels via logical channel groups A computer system for using logical channel groups to indirectly address channels. The computer system includes a processor, a memory, and an input/output (IO)... |
| US-5,568,647 |
Serial control apparatus with a single chip select signal A serial control apparatus is arranged so that an increased number of ICs mounted on a printed circuit card does not increase the number of signal lines for... |
| US-5,568,646 |
Multiple instruction set mapping A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction... |
| US-5,568,645 |
Versatile RF data capture system A data capture system is disclosed as comprising a plurality of client data collection terminals, and a server station. Each terminal including a mechanism for... |
| US-5,568,644 |
Method and apparatus using a tree structure for the dispatching of
interrupts Each device is represented by a node in a hierarchical tree, referred to herein as an interrupt source tree (IST). The root and intermediate nodes of the IST... |
| US-5,568,643 |
Efficient interrupt control apparatus with a common interrupt control
program and control method thereof An interrupt control apparatus using an RISC etc. for performing the same interrupt processing at a plurality of interrupt terminals, which interrupt control... |
| US-5,568,642 |
Computer system with easy programming architecture and programming
method therefor A new and useful computer system facilitates simplification of computer programs establishing a dedicated computer system adapted to a specific task, and makes... |
| US-5,568,641 |
Powerfail durable flash EEPROM upgrade Boot firmware is manipulated within separately erasable/writable blocks of a flash EEPROM, and a non-volatile memory bit circuit is used to force manipulation of... |
| US-5,568,640 |
Document retrieving method in a document managing system A document retrieving method in a document management system which manages documents, using a computer. The classification of documents is managed in accordance... |
| US-5,568,639 |
Method and apparatus for providing an object-oriented file structuring
system on a computer The present invention provides an object-oriented file structuring system. The invention provides a method of defining DATA objects and CONTAINER objects and... |
| US-5,568,638 |
Split control system for a page/page group in a data processing system a
pre-split process using a temporary... A split control system for a page/page group in a data processing system having a storage structure employing a non-dense B-tree cluster structure, includes: a... |
| US-5,568,637 |
Electronic device having pseudo-SRAM and CPU operating in an active mode
and in an idle mode An electronic device uses a pseudo-SRAM having a self-refreshing function, as a memory, and a refresh timing signal having a predetermined period is supplied to... |
| US-5,568,636 |
Method and system for improving a placement of cells using energetic
placement with alternating contraction and... A method of cell placement for an integrated circuit chip includes performing a contraction operation by which at least some of the cells are relocated to new... |
| US-5,568,635 |
Physical memory allocation system, program execution scheduling system,
and information processor A physical memory allocation system comprising an area estimation section, a program modification section, a program size read-in section, a memory size read-in... |
| US-5,568,634 |
Method of writing in a non-volatile memory, notably in a memory card
employing memory allocation strategies on... In a system for the management of non-volatile memories, to avoid losses of information during writing, the critical writing sequences are locked. A back-up... |
| US-5,568,633 |
Process for managing a hierarcy of memories The process for exchanges between the levels in a hierarchy of memories comprising at least one intermediate level in the hierarchy linked to a higher level in... |
| US-5,568,632 |
Method and apparatus for cache memory The present invention is an improved method and apparatus for selecting and replacing a block of a set of cache memory. The present invention provides for the... |
| US-5,568,631 |
Multiprocessor system with a shared control store accessed with
predicted addresses A control store for a microprocessor is divided into two segments with one segment of the control store located on the microprocessor chip and the other segment... |
| US-5,568,630 |
Backward-compatible computer architecture with extended word size and
address space A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also... |
| US-5,568,629 |
Method for partitioning disk drives within a physical disk array and
selectively assigning disk drive... A method for partitioning a disk array into logical storage units distinct from the physical storage units within the array. A set of individual drives within... |
| US-5,568,628 |
Storage control method and apparatus for highly reliable storage
controller with multiple cache memories A storage control unit is connected between a central processing unit having an interface for accessing a first disk unit into which data constructed of a... |
| US-5,568,627 |
Header verification in a disk drive using sector histories for improved
format efficiency A technique for verifying a pre-recorded header in a disk drive uses verification history to protect against errors that can cause verification failure. A head... |
| US-5,568,626 |
Method and system for rewriting data in a non-volatile memory a
predetermined large number of times A method and system for storing data in a non-volatile memory having a plurality of memory regions each assigned with a serial address to permit serial accessing... |
| US-5,568,625 |
Time conversion method of mini discs using multiple time tables A method for converting position data of a mini disc into corresponding regenerating time data of a cluster and a sector in the mini disc system. The method... |
| US-5,568,624 |
Byte-compare operation for high-performance processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data... |
| US-5,568,623 |
Method for rearranging instruction sequence in risc architecture In order to improve the efficiency with which a given set of instructions can be implemented in a RISC architecture environment, the set of instructions are... |
| US-5,568,622 |
Method and apparatus for minimizing the number of control words in a
brom control store of a microprogrammed... Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A... |
| US-5,568,621 |
Cached subtractive decode addressing on a computer bus A local bus subtractive decode device that improves the speed of its subtractive decoding by storing or caching subtractively decoded addresses. At the start of... |
| US-5,568,620 |
Method and apparatus for performing bus transactions in a computer system A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for... |
| US-5,568,619 |
Method and apparatus for configuring a bus-to-bus bridge An information processing system includes a processor for processing information; a processor bus, a first expansion bus; a host bridge for coupling the... |
| US-5,568,618 |
Method and apparatus for controlling and communicating with business
office devices A method and apparatus for controlling and communicating with business office devices, such as copiers, facsimiles and/or printers. The present invention... |
| US-5,568,617 |
Processor element having a plurality of processors which communicate
with each other and selectively use a... A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU... |
| US-5,568,616 |
System and method for dynamic scheduling of 3D graphics rendering using
virtual packet length reduction A system and method for virtually reducing interprocess communication packet size by dynamically redispatching packets for execution. A subcommand dispatching... |
| US-5,568,615 |
Stealth interface for process control computers A stealth interface for an intelligent front-end communication system couples a plurality of actively redundant process control computers to a computer network.... |
| US-5,568,614 |
Data streaming between peer subsystems of a computer system A data handling arrangement for a computer system, with particular application to multimedia systems, allows device adapters (control units) attached to the... |
| US-5,568,613 |
Dataframe bridge filter with communication node recordkeeping A dataframe filter is provided a local area network bridge to monitor the dataframes transmitted on one network to determine those dataframes destined to be... |
| US-5,568,612 |
Method and apparatus for advertising services of two network servers
from a single network node Method and apparatus for advertising two network servers from a single network node in a LAN communication system which supports advertising only a single... |
| US-5,568,611 |
Unauthorized access monitor An information processing system comprises a system processor, an information storage circuit for storing at least programs for operating the information... |
| US-5,568,610 |
Method and apparatus for detecting the insertion or removal of expansion
cards using capacitive sensing A detection system for detecting the insertion or removal of expansion cards having a standard edge connector using one or more capacitive plates coupled to... |
| US-5,568,609 |
Data processing system with path disconnection and memory access failure
recognition A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for... |
| US-5,568,608 |
Method for protecting data in media recording peripheral devices A method for minimizing the loss of data within a data buffer of a peripheral device connected to a host computer upon detection of an error. The peripheral... |
| US-5,568,607 |
Apparatus, systems and methods for controlling power consumption in a
selectively enabled processing system Apparatus, systems and methods are provided for controlling energy consumption by a selectively enabled processing system, such as a high-density code scanner.... |
| US-5,568,606 |
Method and apparatus for maximizing effective disk capacity using
adaptive skewing A DASD array and method wherein spindles in the array are synchronized in speed of rotation and phase. The invention includes a plurality of spindles and at... |
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