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| Patent # | Description |
|---|---|
| US-5,574,952 |
Data storage system and method for operating a disk controller including
allocating disk space for compressed data A data storage system and method for operating a disk controller, and also a disk controller operated in accordance with the method are disclosed. The method... |
| US-5,574,951 |
System for providing a time division random access including a high
speed unidirectional bus and a plurality of... A novel high speed unidirectional bus system is provided for receiving a plurality of novel circuit card assemblies in receptacles on the bus. Adjacent... |
| US-5,574,950 |
Remote data shadowing using a multimode interface to dynamically
reconfigure control link-level and... A remote copy system incorporates dynamically modifiable ports on the storage controllers such that those ports can operate either as a control unit link-level... |
| US-5,574,949 |
Multi-access local area network using a standard protocol for
transmitting MIDI data using a specific data... In a multi-access local area network, a plurality of stations employing a predetermined protocol (e.g., a protocol based on a CSMA/CD system) are linked together... |
| US-5,574,948 |
Method for separating jumpless add-on cards having identical I/O port
onto different I/O ports by using... A method of separating jumpless add-on cards having identical I/O ports onto different I/O ports by first providing a special comparator in the hardware and then... |
| US-5,574,947 |
Data communication cable for a data terminal for simultaneously
connecting multiple peripheral devices and... A splitter cable provides a means for simultaneously connecting a data terminal's communications port to a plurality of peripheral devices. The cable provides... |
| US-5,574,946 |
Data transmission system using independent adaptation processes
associated with storage unit types for directly... A data transmission system between a computer bus and a large number of data storage units connected to one another by a specific connection to which the system... |
| US-5,574,945 |
Multi channel inter-processor coupling facility processing received
commands stored in memory absent status... A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a... |
| US-5,574,944 |
System for accessing distributed memory by breaking each accepted access
request into series of instructions by... A distributed memory I/O interface 10 is provided which allows a plurality of standard peripheral bus I/O controllers 101 to perform multiple transfer operations... |
| US-5,574,943 |
Gate-A20 and CPU reset circuit for mircroprocessor-based computer system A computer system includes a chipset which controls the gate-A20 signal and the CPU RESET signal in a conventional manner in response to commands from a system... |
| US-5,574,942 |
Hybrid execution unit for complex microprocessor A hybrid execution unit for executing miscellaneous instructions in a single clock cycle. The execution unit receives either integer or floating point data, and... |
| US-5,574,941 |
Computer architecture capable of concurrent issuance and execution of
general purpose multiple instruction A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the... |
| US-5,574,940 |
Data processor with quicker latch input timing of valid data A data processing apparatus includes a first data holding circuit, a second data holding circuit, a signal processing circuit, and a control circuit. The first... |
| US-5,574,939 |
Multiprocessor coupling system with integrated compile and run time
scheduling for parallelism In a parallel data processing system, very long instruction words (VLIW) define operations able to be executed in parallel. The VLIWs corresponding to plural... |
| US-5,574,938 |
Allowed operational-link transceiver table verifies the operational
status of transceivers in a multiple... A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data... |
| US-5,574,937 |
Method and apparatus for improving instruction tracing operations in a
computer system A computer processor which provides special bus cycles during tracing operations one of which cycles provides the address of a command on the bus which initiates... |
| US-5,574,936 |
Access control mechanism controlling access to and logical purging of
access register translation lookaside... An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a... |
| US-5,574,935 |
Superscalar processor with a multi-port reorder buffer A multi-port register contains a plurality of cells each capable of storing at least two states. The cells contain at least one read and one write port. Each... |
| US-5,574,934 |
Preemptive priority-based transmission of signals using virtual channels A computer system for transmitting two or more types of signals. Each type of signal is assigned a priority level. Signals of a particular type are transmitted... |
| US-5,574,933 |
Task flow computer architecture A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements.... |
| US-5,574,932 |
One-chip microcomputer and program development/evaluation system therefor A one-chip microcomputer having a mode setting circuit 40a in a first MCU 1a and a second MCU 1b for setting either a first evaluation operation mode under which... |
| US-5,574,931 |
Interconnection process and system for the control of messages in an
array of processors having a parallel... The invention relates to a process for controlling the circulation of messages in a ring network, in which the data are consecutively supplied, which ensures a... |
| US-5,574,930 |
Computer system and method using functional memory A computer system has a central processing unit and a functional memory coupled to the central processing unit's memory access circuitry. The functional memory... |
| US-5,574,929 |
Processor circuit comprising a first processor, a memory and a
peripheral circuit, and system comprising the... Personal computers, a first processor and a second processor belonging to a processor circuit such as a PC card, communicate with one another via a quasi... |
| US-5,574,928 |
Mixed integer/floating point processor core for a superscalar
microprocessor with a plurality of operand buses... A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit... |
| US-5,574,927 |
RISC architecture computer configured for emulation of the instruction
set of a target computer A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an... |
| US-5,574,926 |
One-chip microcomputer system having function for substantially
correcting contents of program A one-chip microcomputer system includes a one-chip microcomputer, a nonvolatile memory which can electrically rewritably store changing data of a program stored... |
| US-5,574,925 |
Asynchronous pipeline having condition detection among stages in the
pipeline A condition detector for an asynchronous pipeline. Each stage in the pipeline includes a storage element for storing a single bit of data indicating whether or... |
| US-5,574,924 |
Vector processing device that utilizes post marks to ensure
serialization of access requests of vector store... A vector processing unit includes a vector unit having a plurality of operation pipelines and a vector register connected to the plurality of operation... |
| US-5,574,923 |
Method and apparatus for performing bi-endian byte and short accesses in
a single-endian microprocessor A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or... |
| US-5,574,922 |
Processor with sequences of processor instructions for locked memory
updates A system and method for executing sequences of instructions which can be used to access a memory location in a locked fashion. The first instruction specifies an... |
| US-5,574,921 |
Method and apparatus for reducing bus noise and power consumption In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the... |
| US-5,574,920 |
Method for controlling power down of a hard disk drive in a computer An integrated device electronics (IDE) driver 40 operating in conjunction with a Basic Input/Output System (BIOS) driver (14), wherein both the IDE driver (40)... |
| US-5,574,919 |
Method for thinning a protocol A method for simplifying computer protocols is disclosed which offers advantages in reducing the memory and processing requirements for invoking the protocol. In... |
| US-5,574,918 |
Method and apparatus for configuring computer program from available
subprograms A graphic program configuration system is described that allows a user to create complete computer programs. In particular, the present invention improves on the... |
| US-5,574,917 |
Method for information communication between concurrently operating
computer programs A method of communication in a computer system is provided for transferring information between multiple, concurrently operating programs, each of which may have... |
| US-5,574,915 |
Object-oriented booting framework An object-oriented framework contains program code for booting a processor with a volatile storage from an attached non-volatile storage. The framework provides... |
| US-5,574,914 |
Method and apparatus for performing system resource partitioning An apparatus and method for managing a number of data processing resources to produce one or more independent and separate data processing partitions. Each... |
| US-5,574,913 |
Control unit for a computer system comprising a plurality of CPU's
having different instruction properties CPUs are grouped into a plurality of groups of CPUs. CPUs of a particular group have a similar instruction configuration, but their instruction properties are... |
| US-5,574,912 |
Lattice scheduler method for reducing the impact of covert-channel
countermeasures A method for scheduling processes for execution in a computer system organizes the processes into run queues in accordance with the respective secrecy classes of... |
| US-5,574,911 |
Multimedia group resource allocation using an internal graph An intelligent system for the efficient selection and allocation of the various types of resources available in a multimedia environment. The system interrelates... |
| US-5,574,910 |
Method for segmenting data packets to form binary decision trees which
determine filter masks combined to... A packet processing method and apparatus efficiently process a binary data packet based upon information contained in the header portion of the packet. The... |
| US-5,574,909 |
Apparatus and method for data search using selected or representative
data sample The invention relates to searching for a desired data item within a group of data. Representative samples among a group of data to be searched are displayed, and... |
| US-5,574,908 |
Method and apparatus for generating a query to an information system
specified using natural language-like... Computerized tools for modeling database designs and specifying queries of the data contained therein. Once it is determined that an information system needs to... |
| US-5,574,907 |
Two-pass defragmentation of compressed hard disk data with a single data
rewrite A method and apparatus for defragmenting compressed file data stored on a disk. The method includes a first pass in which the FAT and MDFAT entries for each file... |
| US-5,574,906 |
System and method for reducing storage requirement in backup subsystems
utilizing segmented compression and... In a client/server environment, a method and means for reducing the storage requirement in the backup subsystem and further reducing the load on the transmission... |
| US-5,574,905 |
Method and apparatus for multimedia editing and data recovery A specialized linked-list editing structure is used to order multimedia file segments in a multimedia file to be edited. Each multimedia file segment is... |
| US-5,574,904 |
Database management system in an intelligent network using a common
request data format A service control point of an intelligent telephone network has an application interface platform for managing a database and a plurality of service application... |
| US-5,574,903 |
Method and apparatus for handling request regarding information stored
in a file system In a computer including at least one caller adapted to request access to a storage media, the storage media being organized according to one of at least one file... |
| US-5,574,902 |
Efficient destaging of updated local cache pages for a transaction in a
multisystem and multiprocess database... An efficient procedure for determining the set of buffer pool database pages that must be externalized to stable storage and for scheduling their write I/O's... |
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