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| Patent # | Description |
|---|---|
| US-5,574,901 |
Method and apparatus for object traversing suitable for structured
memory formed by linked objects An object traversing scheme in which the traverse procedure and the traverse rights can be specified flexibly. In this scheme, the object is stored with an... |
| US-5,574,900 |
System and method for optimizing parallel processing of database queries The present invention provides a system and method for retrieving data from a computerized database system. Prior to execution of a query statement, the system... |
| US-5,574,899 |
Generation number managing apparatus for adjusting generation numbers
among processors or program files A generation number managing apparatus for adjusting generation numbers among processors or program files in a multiprocessor system, includes: a generation... |
| US-5,574,898 |
Dynamic software version auditor which monitors a process to provide a
list of objects that are accessed A data processing system and method features an object selector including an auditor for recording, as an audit record, which versions of objects are accessed by... |
| US-5,574,897 |
System managed logging of objects to speed recovery processing System control over the logging of objects in order to meet the user specified recovery requirements. Under the fixed recovery time environment, the user chooses... |
| US-5,574,896 |
Framing circuit that increases the pulse width of the byte clock signal
after the byte clock signal is reset A framing circuit, which frames bytes of data received from a serial data bit stream, prevents a short byte clock pulse from being formed when the byte clock... |
| US-5,574,895 |
Multi-memory function programmable counter and timer A multi-memory function programmable counter or multi-memory function programmable timer capable of selectively assuming a plurality of counter or timer... |
| US-5,574,894 |
Integrated circuit data processor which provides external sensibility of
internal signals during reset An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in... |
| US-5,574,893 |
Computer logic simulation with dynamic modeling A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a... |
| US-5,574,892 |
Use of between-instruction breaks to implement complex in-circuit
emulation features A processor uses between-instruction in-circuit emulation breaks to implement complex in-circuit emulation features. The processor uses a bit in hardware that... |
| US-5,574,891 |
Method for managing the input codes from keyboard and pointing device A method for managing the input codes from the keyboard and the point device and an apparatus thereof are provided. When the computer system is not coupled to a... |
| US-5,574,890 |
Computer design tool for rotary slitting of metal and a method of use
thereof A computer design tool for determining a predictive indication of slit width variation to adjust an arbor setup in rotary slitting of metal in accordance with... |
| US-5,574,889 |
Apparatus for selecting and evaluating design based on stored information The invention is a design evaluation apparatus for evaluating a design composed of a plurality of design elements. The apparatus has a database stored therein.... |
| US-5,574,888 |
A method and apparatus for establishing compatibility between
communication applications producing at commands... An interface for enabling data communication software applications previously sold in the commercial marketplace to utilize a Telephony Application Programming... |
| US-5,574,887 |
Apparatus and method for emulation routine pointer prefetch An apparatus and method for emulation routine pointer prefetch are disclosed. The apparatus includes an emulated program counter (EPC), a prefetch state machine,... |
| US-5,574,886 |
Data processing system for encoding and compressing a pattern data and
for decoding the encoded and compressed... An information processing apparatus includes a change point detection unit for obtaining dot change point positions and the number of change points in units of... |
| US-5,574,885 |
Modular buffer memory with separately controllable logical output queues
for use in packet switched networks A modular system for a buffer memory used for storing output queues (80a-k) of a packet switch is described. A series of memories (90) are each connected to both... |
| US-5,574,884 |
DRAM control circuit A DRAM control circuit according to the present invention, comprising a DRAM, a DRAM controller adapted for receiving an address, write data, and a data rewrite... |
| US-5,574,883 |
Single chip processing unit providing immediate availability of
frequently used microcode instruction words A multi-cache memory system resides on-chip with a system interface to external memory. A general cache memory holds frequently used data and OPCODES for... |
| US-5,574,882 |
System and method for identifying inconsistent parity in an array of
storage A system and method are provided that is used by software implemented Redundancy Array of Inexpensive Disk (RAID) arrays to achieve adequate performance and... |
| US-5,574,881 |
High capacity data storage method and system using independently
controlled heads and circuitry for monitoring... A fast access high capacity data storage system and method are disclosed, the data storage system including a disk-based storage system employing a plurality of... |
| US-5,574,880 |
Mechanism for performing wrap-around reads during split-wordline reads A memory with at least two banks, each bank capable of storing N=2.sup.n unique lines of data, each lines of data addressable by an n-bit code corresponding to... |
| US-5,574,879 |
Addressing modes for a dynamic single bit per cell to multiple bit per
cell memory A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address... |
| US-5,574,878 |
Method of parallel purging of translation lookaside buffer in a
multilevel virtual machine system A method fr purging a translation lookaside buffer purges only those entries required to be purged in order to eliminate overhead incurring degradation in the... |
| US-5,574,877 |
TLB with two physical pages per virtual tag A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible... |
| US-5,574,876 |
Processor system using synchronous dynamic memory A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a node register for determining an operation mode, a main storage... |
| US-5,574,875 |
Cache memory system including a RAM for storing data and CAM cell arrays
for storing virtual and physical addresses A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each... |
| US-5,574,874 |
Method for implementing a checkpoint between pairs of memory locations
using two indicators to indicate the... A method for memory checkpointing which does not involve copying of data and that is virtually instantaneous involves designating the active location at a... |
| US-5,574,873 |
Decoding guest instruction to directly access emulation routines that
emulate the guest instructions A system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at... |
| US-5,574,872 |
Method and apparatus for controlling the saving of pipelines in
pipelined processors during trap handling A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating... |
| US-5,574,871 |
Method and apparatus for implementing a set-associative branch target
buffer A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target... |
| US-5,574,870 |
Method for the commissioning of an interface to be allocated to
different transmission paths in a... ISDN basic interface S.sub.o of an ISDN communication system that can be connected to an S.sub.o interface of an ISDN communication terminal equipment or of an... |
| US-5,574,869 |
Bus bridge circuit having configuration space enable register for
controlling transition between various modes... A configuration space enable/disable mechanism for transferring configuration data to and from peripheral components coupled to one or more peripheral component... |
| US-5,574,868 |
Bus grant prediction technique for a split transaction bus in a
multiprocessor computer system A early bus grant prediction technique combines the operating advantages of both a split transaction bus and a simple shared bus. When a read request is... |
| US-5,574,867 |
Fast first-come first served arbitration method A first-come-first-serve ("FCFS") scheduler that routes requests from two or more clients to a single resource. The FCFS scheduler contains a time stamp... |
| US-5,574,866 |
Method and apparatus for providing a data write signal with a
programmable duration A control circuit which allows computer systems to modify signal timing relationships in the hardware via programmable ports in the system, thereby allowing... |
| US-5,574,865 |
System for data transfer protection during module
connection/disconnection onto live bus A plurality of digital modules on a Futurebus Plus common system bus means in a network are connected by the Futurebus Plus system bus for transfer of data... |
| US-5,574,864 |
Method of implementing EISA bus devices on a host bus by disabling
bridge circuitry between host and EISA buses In a computer system with a host bus and an EISA bus, devices typically implemented on an EISA bus are instead implemented on a host bus. These devices are still... |
| US-5,574,863 |
System for using mirrored memory as a robust communication path between
dual disk storage controllers In a disk storage system having dual controllers and mirrored memory therebetween, the mirrored memory is used to establish a robust communication path between... |
| US-5,574,862 |
Multiprocessing system with distributed input/output management A multiprocessing system uses remote file managers associated with each remote processor to prepare data for storage in a disk storage array. The data are then... |
| US-5,574,861 |
Dynamic allocation of B-channels in ISDN An implementation of an ISDN router enables computers interconnected to each other and to the ISDN to share resources by issuing operating system commands. One... |
| US-5,574,860 |
Method of neighbor discovery over a multiaccess nonbroadcast medium A technique for generating, distributing and maintaining a list of operational nodes in a network using a nonbroadcast communication medium, wherein the nodes... |
| US-5,574,859 |
Method and apparatus for using a software configurable connector to
connect a palmtop computer having a custom... A portable information storage and transfer device for use with IC memory card-based portable computers performs many data transfer operations. The floppy disk... |
| US-5,574,858 |
Method and apparatus for, upon receipt of data from a mouse, requiring
the remainder of data needed to... A method of operating a computer which has a CPU, an input/output coprocessor, and an attached pointing device, the input/output coprocessor receiving data in... |
| US-5,574,857 |
Error detection circuit for power up initialization of a memory array A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and... |
| US-5,574,856 |
Fault indication in a storage device array Method and apparatus are disclosed for providing an indication relating to certain faults that can occur during data storing operations in an array storage... |
| US-5,574,855 |
Method and apparatus for testing raid systems An error injection test scripting system that permits a test engineer to select from a series of commands those that will induce a desired test scenario. These... |
| US-5,574,854 |
Method and system for simulating the execution of a computer program A simulation system to simulate the execution of a computer program. The computer program is developed for invoking operating system functions of a first... |
| US-5,574,853 |
Testing integrated circuit designs on a computer simulation using
modified serialized scan patterns A method to test an integrated circuit design on a computer simulation loads a desired simulation test vector in parallel into a scan chain (30). The simulation... |
| US-5,574,852 |
Integrated microcontroller having a cup-only mode of operation which
directly outputs internal timing... For use by an emulation circuit, a non-special-custom microcontroller multiplexes a port among user data and program store addresses. It has a multistate machine... |
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