Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-5,574,701 |
Marble watch A timepiece is included in a marble which is rotatably mounted on a watchcase. The marble is easily removed from the watchcase to be usable in all games that... |
| US-5,574,700 |
Ratchet operated kick-up bracket A mounting apparatus for mounting a sonar transducer assembly to an aquatic vehicle, particularly for fish finding and mapping devices. The mounting apparatus... |
| US-5,574,699 |
Fiber optic lever towed array A small diameter towed acoustic line array comprising a plurality of miniature fiber optic lever hydrophones spaced at preselected locations along the array and... |
| US-5,574,698 |
Ram row decode circuitry that utilizes a precharge circuit that is
deactivated by a feedback from an activated... A precharge circuit which is deactivated once a word line driver is activated. Specifically, a low output signal created by the selected driver is fed back to... |
| US-5,574,697 |
Memory device with distributed voltage regulation system A memory device includes a memory cell array, control circuits, and a voltage regulation system. The voltage regulation system includes an array power bus... |
| US-5,574,696 |
Dynamic ram device having high read operation speed In a dynamic random access memory device including a plurality of word lines, a plurality of bit lines, and a plurality of dynamic memory cells connected to the... |
| US-5,574,695 |
Semiconductor memory device with bit line load circuit for high speed
operation A semiconductor memory has memory cells for data storage, connected to bit line pair a memory cell selection decoder for selecting the memory cell in the... |
| US-5,574,694 |
Integrated semiconductor memory circuit and method for its operation In an integrated semiconductor memory circuit and a method for its operation, the circuit includes devices by means of which second electrodes of memory... |
| US-5,574,693 |
Semiconductor memory device A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption... |
| US-5,574,692 |
Memory testing apparatus for microelectronic integrated circuit A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a... |
| US-5,574,691 |
Semiconductor memory device having circuit for activating predetermined
rows of memory cells upon detection of... When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory... |
| US-5,574,690 |
Self-test device for memories, decoders, etc. A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix... |
| US-5,574,689 |
Address comparing for non-precharged redundancy address matching An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one... |
| US-5,574,688 |
Apparatus and method for mapping a redundant memory column to a
defective memory column A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell... |
| US-5,574,687 |
Semiconductor memory There is disclosed a rapidly and correctly readable semiconductor device wherein a clamping transistor (Pcr.sub.-- 0) having a threshold voltage (Vthp)... |
| US-5,574,686 |
Nonvolatile semiconductor storage system An object is to realize a nonvolatile semiconductor storage system which can prevent a false reading operation due to the overerasure, improve the lower limit of... |
| US-5,574,685 |
Self-aligned buried channel/junction stacked gate flash memory cell An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent... |
| US-5,574,684 |
Flash memory having data refresh function and data refresh method of
flash memory A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address... |
| US-5,574,683 |
Memory device and a method for writing information in the memory device A memory device comprises a row address signal line Ax, a pair of column address signal lines Ay1, Ay2, a standby signal line Sb, a memory cell provided at an... |
| US-5,574,682 |
PC card A PC card comprising a housing having side surfaces and a connector surface communicating with the side surfaces, contact holes mated with contact pins of a... |
| US-5,574,681 |
Method for DRAM sensing current control A DRAM having a plurality of bit lines and associated sense amplifiers, the bit lines being arrayed across an integrated circuit chip and the sense amplifiers... |
| US-5,574,680 |
Semiconductor memory device A semiconductor memory device including a memory cell array which is formed of each of memory cells connected to intersection of a plurality of bit lines and... |
| US-5,574,679 |
Memory data protection for a ferroelectric memory A nonvolatile ferroelectric memory device comprises a power supply and a memory cell array having a plurality of memory cells arranged in rows and columns and... |
| US-5,574,678 |
Continuous time programmable analog block architecture A programmable analog circuit apparatus receives a differential analog input signal and provides a processed differential analog output signal. The programmable... |
| US-5,574,677 |
Adaptive non-restoring integer divide apparatus with integrated overflow
detect The number of steps to perform integer division is reduced by combining detection of a remainder overflow with the final remainder restore step. When the sign... |
| US-5,574,676 |
Integer multiply instructions incorporating a subresult selection option A computer instruction and apparatus for performing a N-bit by N-bit multiplication and having the ability to select a part of the multiplication result for... |
| US-5,574,675 |
State-controlled half-parallel array walsh transform A Fast Walsh Transform (FWT) processor is disclosed, based on Good's factorization, which reduces the number of adder/subtractor units to (N/2), where N is the... |
| US-5,574,674 |
Fourier transform processing for digital filters or other spectral
resolution devices A process for suppressing the Gibbs phenomenon in a train of digital signals when such signals are undergoing a discrete Fourier transform or a fast Fourier... |
| US-5,574,673 |
Parallel architecture for generating pseudo-random sequences A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of... |
| US-5,574,672 |
Combination multiplier/shifter A combination multiplier/shifter circuit (FIG. 2) can be used to implement an arithmetic or execution unit, using the multiplier/shifter to perform both... |
| US-5,574,671 |
True/complementer for a half-band filter A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing... |
| US-5,574,670 |
Apparatus and method for determining a number of digits leading a
particular digit When a data input signal having R plus X groups of M digits is received, the digits are segmented such that X different first counter-detectors receive M digits... |
| US-5,574,669 |
Device for measuring foot motion and method A device and method of measuring the speed of an object such as a foot is provided which can accurately determine lateral or other movements. The device employs... |
| US-5,574,668 |
Apparatus and method for measuring ball grid arrays An array of touch sensors are brought in contact with a ball grid array. A linear actuator moves the array of touch sensors. The position of the linear actuator... |
| US-5,574,667 |
Temperature independent fan-error correction circuit A computer system has control circuitry for detecting directly and independently of temperature the malfunctioning of a fan used for cooling the housing of the... |
| US-5,574,666 |
Color printing method and apparatus using gamut mapping in Munsell space A method and apparatus for constructing a color printer table. Printable colors in CIELAB space are transformed to Munsell space and color mapping functions are... |
| US-5,574,665 |
Receiver apparatus and method for frequency tagging The present invention is a system and method for resolving closely spaced frequencies in frequency patterns used to tag objects. The system comprises a base... |
| US-5,574,664 |
Method for calibrating computer monitors used in the printing and
textile industries An apparatus for calibrating color settings of a computer monitor to cause a proofed image, i.e., a prepress image, to essentially match a printed image on a... |
| US-5,574,663 |
Method and apparatus for regenerating a dense motion vector field The present invention provides a method (300) and apparatus (100) for regenerating a dense motion vector field, which describes the motion between two temporally... |
| US-5,574,662 |
Disk-based digital video recorder A digital video recorder employing standard hard disk arrays employs a caching system to enable continuous video data to be supplied to and provided from the... |
| US-5,574,661 |
System and method for inverse discrete cosine transform implementation An apparatus and method for calculation of the inverse discrete cosine transform for image decompression are disclosed. The apparatus may be implemented with... |
| US-5,574,660 |
Communication method and apparatus A method and apparatus for operating a radio for communicating between a terrestrial station and a satellite by (i) selecting one of a number of predetermined... |
| US-5,574,659 |
Dye transfer prints utilizing digital technology Motion picture prints made with the dye transfer, or imbibition (IB) process have a reputation for superior image quality and permanence. The process offers... |
| US-5,574,658 |
Method of designing optimum skeleton and plate structures A method of designing an optimum skeleton structure uses a computer to obtain a skeleton structure from a density distribution within a 2 or 3 dimensional design... |
| US-5,574,657 |
Electronic rate meter controller and method An electronic rate meter controller is provided for controlling the dispensing of meterable material by an applicator apparatus, typically in the agricultural... |
| US-5,574,656 |
System and method of automatically generating chemical compounds with
desired properties A computer based, iterative process for generating chemical entities with defined physical, chemical and/or bioactive properties. During each iteration of the... |
| US-5,574,655 |
Method of allocating logic using general function components A method is described for configuring a general symbol to represent a specific symbol indicated by a user. The specific symbols are part of a library. A general... |
| US-5,574,654 |
Electrical parameter analyzer An electrical parameter analyzer analyzes samples of electrical power by executing program instructions stored on a PCMCIA compatible program card. The analyzer... |
| US-5,574,653 |
Switchboard A switchboard having a mains power input circuit (A,N) and a plurality of output circuits (HOT WATER, OFF PEAK, OVEN, LIGHT, POWER2, POWER1) and including a... |
| US-5,574,652 |
Automated control system for machine tool A control system for controlling multiple operations of a machine tool includes an electronic controller. The controller is programmed to execute sequences of... |
Copyright 2008−2012 Patents.com
