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| Patent # | Description |
|---|---|
| US-5,581,754 |
Methodology for managing weakly consistent replicated databases Write operations for weakly consistent replicated database systems have embedded conflict detection and conflict resolution procedures for identifying and... |
| US-5,581,753 |
Method for providing session consistency guarantees The present invention provides client-selected consistency guarantees to clients of a weakly consistent replicated database on a per "session" basis. The clients... |
| US-5,581,752 |
Electronic document retrieval and display system and method of
retrieving electronically stored documents The present invention provides an electronic document filing system. The electronic document filing system comprises a document database for storing document, an... |
| US-5,581,751 |
Key extraction apparatus and a key extraction method A key extraction apparatus comprises a main memory, a data input unit of the key extraction apparatus, a data-write controller which generates a data-write... |
| US-5,581,750 |
System and method for improving data recovery performance A system and method are provided for recovering a computerized database. During transaction processing of a database, at least one log range is tracked... |
| US-5,581,749 |
System and method for maintaining codes among distributed databases
using a global database A global code system maintains reference records for multiple transaction processing systems on a central database (called a global code database). A client... |
| US-5,581,748 |
Phase register for synchronization of multiple signal processors In a computer system having two processors both of which are used to process frames, a method for synchronizing a first set of frames corresponding to the first... |
| US-5,581,747 |
Communication system for programmable devices employing a circuit shift
register An interface system for communicating between a programmable device, such as a hearing assisting device, and a programmer unit employs a circular shift register... |
| US-5,581,746 |
Synchronous LSI memory device A synchronous LSI memory device, comprises memory cell array sections (BK1, BK2) each having a plurality of memory cells; a timing generating section (CLOCK... |
| US-5,581,745 |
Apparatus for suspending the bus cycle of a microprocessor by inserting
wait states An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a... |
| US-5,581,744 |
Method and apparatus for correcting polarity using a synchronizing
sequence A method and apparatus for improving communication capability between computer devices and peripherals scans a data signal for a valid synchronizing sequence. If... |
| US-5,581,743 |
CKD to fixed block mapping for optimum performance and space utilization Count-key-data records are mapped to a fixed-block architecture storage device using a fuzzing packing method that packs some count-key-data records while... |
| US-5,581,742 |
Apparatus and method for emulating a microelectronic device by
interconnecting and running test vectors on... A simulation system for a microelectronic device having two or more functional modules from a megacell library, the simulation system utilizing actual physically... |
| US-5,581,741 |
Programmable unit for controlling and interfacing of I/O busses of
dissimilar data processing systems A programmable I/O bus adapter for interfacing and controlling two data processing systems having dissimilar and incompatible architectures. The programmable I/O... |
| US-5,581,740 |
System for reading CD ROM data from hard disks A CD ROM server comprises a CD ROM drive and an array of hard disk drives. Means are provided for copying data from the CD ROM drive to the array of hard disk... |
| US-5,581,739 |
Two lane computing systems A dual lane computing system has at least one processor in each lane, each processor having an associated store which stores input data supplied to the processor... |
| US-5,581,738 |
Method and apparatus for back-annotating timing constraints into
simulation models of field programmable gate... A method and apparatus for back-annotating timing constraints onto a logical simulation model of a field programmable gate array circuit includes a process and... |
| US-5,581,737 |
Method and apparatus for expansion, contraction, and reapportionment of
structured external storage structures A method and apparatus for optimizing a data structure of an external data storage facility shared by a plurality of data processing systems, the data structure... |
| US-5,581,736 |
Method and system for dynamically sharing RAM between virtual memory and
disk cache In a computer system having a processing unit, a primary memory space (RAM) and a secondary memory space (disk), the primary memory space being allocated between... |
| US-5,581,735 |
System for supplying unit image data to requesting users from multiple
storage devices based on directory... The invention uses a storage device effectively to supply data to as many user terminals as possible. Sub-control units read unit data in which dynamic image... |
| US-5,581,734 |
Multiprocessor system with shared cache and data input/output circuitry
for transferring data amount greater... A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing... |
| US-5,581,733 |
Data transfer control of a video memory having a multi-divisional random
access memory and a multi-divisional... An image memory has a random access memory array capable of being randomly accessed; a serial access memory array partitioned into 2.sup.n (n>1) divisional... |
| US-5,581,732 |
Multiprocessor system with reflective memory data transfer device A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved... |
| US-5,581,731 |
Method and apparatus for managing video data for faster access by
selectively caching video data A method and apparatus for decreasing computer fetch time utilizes cache memory to store video data when the data is not modified by a write modifier. The video... |
| US-5,581,730 |
Condition detector and prioritizer with associativity determination logic A device for simultaneously detecting more than one condition, where each condition corresponds to a specific memory cell of an array of more than one memory... |
| US-5,581,729 |
Parallelized coherent read and writeback transaction processing system
for use in a packet switched cache... A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module,... |
| US-5,581,728 |
Information storage system having advance reading function A reading unit reads first data blocks among the data blocks stored in an information storage medium according to the information specified by a mother system. A... |
| US-5,581,727 |
Hierarchical cache system flushing scheme based on monitoring and
decoding processor bus cycles for flush/clear... An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU... |
| US-5,581,726 |
Control system for controlling cache storage unit by using a
non-volatile memory A control system controls a disk unit and a cache storage unit having a cache memory and a nonvolatile memory based on a writing instruction supplied from a host... |
| US-5,581,725 |
Cache memory system having first and second direct-mapped cache memories
organized in hierarchical structure A microprocessor includes a CPU, a main memory and primary and second cache memories of the direct mapped type, that are all implemented on the same LSI chip.... |
| US-5,581,724 |
Dynamically mapped data storage subsystem having multiple open destage
cylinders and method of managing that... A data storage subsystem dynamically maps a virtual data storage device image presented to associated processors to physical data storage devices used to... |
| US-5,581,723 |
Method and apparatus for retaining flash block structure data during
erase operations in a flash EEPROM memory... A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory... |
| US-5,581,722 |
Memory management unit for managing address operations corresponding to
domains using environmental control A memory management unit (MMU) for controlling a CPU's right to access a memory in order to initiate performance of an operation. The MMU includes a translator... |
| US-5,581,721 |
Data processing unit which can access more registers than the registers
indicated by the register fields in an... The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction,... |
| US-5,581,720 |
Apparatus and method for updating information in a microcode instruction In a computer for executing a computer program, apparatus and a method for updating information within a computer program instruction without interrupting... |
| US-5,581,719 |
Multiple block line prediction A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction... |
| US-5,581,718 |
Method and apparatus for selecting instructions for simultaneous
execution A method and apparatus for selecting instructions from a sequence of undifferentiated bytes of instruction data is described. A first plurality of sequential... |
| US-5,581,717 |
Decoding circuit and method providing immediate data for a
micro-operation issued from a decoder Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which... |
| US-5,581,716 |
IDE type CD-ROM drive interfacing circuit An interface circuit for an IDE-type CD-ROM drive connected to a personal computer using a standard IDE interface according to a hard disk drive interface... |
| US-5,581,715 |
IDE/ATA CD drive controller having a digital signal processor interface,
dynamic random access memory, data... A compact disk drive controller to control the access of information from an optical compact disk (CD) digital data storage device by a host computer using an... |
| US-5,581,714 |
Bus-to-bus read prefetch logic for improving information transfers in a
multi-bus information handling system... A method and system for improving bus-to-bus data transfers in a multi-bus computer system is provided. The system includes a system bus having a slave device... |
| US-5,581,713 |
Multiprocessor computer backplane bus in which bus transactions are
classified into different classes for... A computer having multiple modules connected by a backplane bus includes multiple competition signal lines and multiple class signal lines. Access to the... |
| US-5,581,712 |
Method and apparatus for managing live insertion of CPU and I/O boards
into a computer system Circuitry and logic are provided to a bus control module of a system bus of a computer system to inject the bus control module into, and win a system test master... |
| US-5,581,711 |
Method and apparatus for determining the number of words of transferred
data in a digital data transfer system An apparatus and method for transferring digital data is herein disclosed using a central processing unit and a direct memory access controller. Based on the... |
| US-5,581,710 |
Full duplex communication on a single communication ring A ring network of workstations interconnected on a single simplex ring is converted to duplex communications on the single ring by placing two transceivers in... |
| US-5,581,709 |
Multiple computer system using I/O port adaptor to selectively route
transaction packets to host or shared I/O... In a computer system of the present invention, CPUs of a single or a plurality of host computers access the shared IO devices connected to a shared IO bus of... |
| US-5,581,708 |
Data transmission system using electronic apparatus having a plurality
of transmission protocols In a data transmission system, a card reader/writer provided in a terminal device and an IC card are connected through a contact unit, the IC card is started in... |
| US-5,581,707 |
System for wireless collection of data from a plurality of remote data
collection units such as portable bar... In order to collect data messages at a base station which is in radio communications with portable data collection terminals, such as bar code readers, that may... |
| US-5,581,706 |
Method forming an audio/video interactive data signal A method and apparatus for generating an interactive component data stream, representing an application program, for an audio video interactive (AVI) composite... |
| US-5,581,705 |
Messaging facility with hardware tail pointer and software implemented
head pointer message queue for... A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed... |
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