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| Patent # | Description |
|---|---|
| US-5,580,846 |
Surface treating agents and treating process for semiconductors The concentration of Al on silicon surface is reduced to lose its influence on the growth rate of an oxide film during thermal oxidation when semiconductor... |
| US-5,580,845 |
Lubricant A lubricant suitable for use in an industrial forming process, especially cold pilgering, comprises a polyglycol as base fluid, a water-soluble inorganic filler... |
| US-5,580,844 |
Encapsulated breaker chemical According to the present invention, there is provided a coated breaker chemical in which the coating comprises a blend of a neutralized sulfonated ionomer and... |
| US-5,580,843 |
Substituted 1-arylpyrazoles The invention relates to new substituted 1-arylpyrazoles of the general formula (I) ##STR1## to a plurality of processes for their preparation, and to their... |
| US-5,580,842 |
N-azinyl-N'-(het)arylsulphonyl-ureas N-azinyl-N'-(het)arylsulphonyl-ureas of the formula (I): ##STR1## in which J represents a 5,6-dihydro-[1,4,2]-dioxazin-3-ylaryl or-hetaryl radical; A... |
| US-5,580,841 |
Solid, phytoactive compositions and method for their preparation Disclosed are solid, phytoactive, N-phosphonomethyl-N-carboxymethyl compositions. Also disclosed are processes for the preparation of such compositions by (a)... |
| US-5,580,840 |
Method and composition for preservation of cut flowers A method of preserving cut flowers such as roses, tulips, carnations and mums, by the insertion of the freshly cut stems of cut flowers in a solution of a... |
| US-5,580,839 |
Binary ferrihydrite catalysts A method of preparing a catalyst precursor comprises dissolving an iron salt and a salt of an oxoanion forming agent, in water so that a solution of the iron... |
| US-5,580,838 |
Uniformly plated microsphere catalyst Cross-linked polymer microspheres having a sulfonated cation exchange surface are carefully separated into fractions of equal size and density. Each fraction is... |
| US-5,580,837 |
Ceramic material for use in casting reactive metals An improved sintered ceramic core is used in a mold during the casting of a reactive metal. Prior to sintering, the core contains ceramic material which includes... |
| US-5,580,836 |
Group IVB based materials A densified titanium diboride based ceramic composition is provided having W and Co therein and a fine grain size. The composition has particular usefulness as a... |
| US-5,580,835 |
Ceramic fibers produced by electrophoretic deposition of particles Ceramic fibers may be produced by the electrophoretic deposition of metal oxide upon a conductive fiber core, which core may be subsequently removed. |
| US-5,580,834 |
Self-sintered silicon carbide/carbon graphite composite material having
interconnected pores which may be... A self-sintered silicon carbide/carbon-graphite composite material having interconnected pores which may be impregnated, and a raw batch and process for... |
| US-5,580,833 |
High performance ceramic composites containing tungsten carbide
reinforced chromium carbide matrix A high performance ceramic composite containing tungsten carbide reinforced chromium carbide matrix in which 5.about.35 vol % of tungsten carbide particles are... |
| US-5,580,832 |
Method for obtaining high density green ceramics from powders A method of forming a highly dispersed ceramic powder slurry is provided prising forming an aqueous based slurry of a ceramic powder and a polyelectrolyte at an... |
| US-5,580,831 |
Sawcut method of forming alignment marks on two faces of a substrate The present invention is a method for producing alignment marks on opposite faces of a generally flat substrate such as a semiconductor wafer. First, reference... |
| US-5,580,830 |
Modified reaction chamber and improved gas flushing method in rapid
thermal processing apparatus A reaction chamber for a Rapid Thermal Processing (RTP) system contains an aperture to allow introduction and removal of the object to be processed. The cross... |
| US-5,580,829 |
Method for minimizing unwanted metallization in periphery die on a
multi-site wafer A method and apparatus for providing a mask (200) on a multi-site wafer (100) is accomplished by first creating a first mask key (204) which contains... |
| US-5,580,828 |
Method for chemical surface passivation for in-situ bulk lifetime
measurement of silicon semiconductor material Minority carrier bulk lifetime maps are accomplished using in-situ .mu.-PCD measurement techniques on a non-oxidized Si specimen of either polarity. Surface... |
| US-5,580,827 |
Casting sharpened microminiature tips Sharpened microminiature tips are produced by casting in a silicon/silicon dioxide mold. The silicon dioxide layer is formed by exposing cavities in a single... |
| US-5,580,826 |
Process for forming a planarized interlayer insulating film in a
semiconductor device using a periodic resist... In a process for manufacturing a semiconductor device, on a surface including interconnections selectively formed on an insulating film, an interlayer insulating... |
| US-5,580,825 |
Process for making multilevel interconnections of electronic components A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate... |
| US-5,580,824 |
Method for fabrication of interconnections in semiconductor devices An interconnection pattern of a Cr film is defined by a wet-etching process by using fluoric acid and then a Cu film is grown over the surface of the Cr film. It... |
| US-5,580,823 |
Process for fabricating a collimated metal layer and contact structure
in a semiconductor device A process for fabricating a semiconductor device which includes forming a collimated metal layer (54) on the surface of a semiconductor substrate (24), while... |
| US-5,580,822 |
Chemical vapor deposition method A starting gas feeding apparatus for forming a gaseous starting material from a liquid starting material and feeding the gaseous starting material into a... |
| US-5,580,821 |
Semiconductor processing method of forming an electrically conductive
contact plug A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical... |
| US-5,580,820 |
Method of forming a semiconductor material having a substantially I-type
crystalline layer A method for forming a semiconductor material involves forming an i-type non-single crystalline layer on a substrate and crystallizing the semiconductor material... |
| US-5,580,819 |
Coating composition, process for producing antireflective coatings, and
coated articles Describes a composition for producing durable coatings and a process for preparing a single-layer broad band antireflective coating on solid substrates, such as... |
| US-5,580,818 |
Fabrication process for semiconductor optical device A SiO.sub.2 mask is formed on an n-type InP substrate. The mask gap width is narrower in a region I (laser region) and wider in a region II (modulator region).... |
| US-5,580,817 |
Valve assembly A valve assembly for a discharge device, in particular a steering pump, including a flow control valve for controlling flow from the discharge device to an... |
| US-5,580,816 |
Local oxidation process for high field threshold applications A method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The ... |
| US-5,580,815 |
Process for forming field isolation and a structure over a semiconductor
substrate An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous... |
| US-5,580,814 |
Method for making a ferroelectric memory cell with a ferroelectric
capacitor overlying a memory transistor A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of... |
| US-5,580,813 |
Method of forming a semiconductor memory device having a contact region
between memory cell and an interlayer... A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The... |
| US-5,580,812 |
Semiconductor device have a belt cover film The conductive material film, e.g. a polysilicon film, is anisotropically etched for forming a pattern, e.g. a storage electrode, and a base insulating film,... |
| US-5,580,811 |
Method for the fabrication of a semiconductor memory device having a
capacitor A method for the fabrication of a semiconductor device, capable of reducing the step between the cell region and the peripheral circuit region by forming a... |
| US-5,580,810 |
Method of making a semiconductor memory device A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell... |
| US-5,580,809 |
Method of making a mask ROM using tunnel current detection to store data Each of the portions corresponding to the crossings of a plurality of first strip conductive layers serving as bit lines and a plurality of second strip... |
| US-5,580,808 |
Method of manufacturing a ROM device having contact holes treated with
hydrogen atoms and energy beam A method for manufacturing a mask ROM by first forming a contact hole with a semiconductor within. A surface treatment is then applied to supply by hydrogen... |
| US-5,580,807 |
Method of fabricating a high voltage MOS transistor for flash EEPROM
applications having a uni-sided lightly... High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide... |
| US-5,580,806 |
Method of fabricating a buried contact structure for SRAM A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned... |
| US-5,580,805 |
Semiconductor device having various threshold voltages and manufacturing
same An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+... |
| US-5,580,804 |
Method for fabricating true LDD devices in a MOS technology A method of fabricating a true-LDD MOS transistor is described. The fabrication method includes the step of forming an LDD photoresist mask layer on a... |
| US-5,580,803 |
Production method for ion-implanted MESFET having self-aligned lightly
doped drain structure and T-type gate A production method for ion-implanted MESFET having self-aligned LDD structure and T-type gate, that the reverse mesa portion is formed at a predetermined part... |
| US-5,580,802 |
Silicon-on-insulator gate-all-around mosfet fabrication methods A silicon-on-insulator (SOI) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by... |
| US-5,580,801 |
Method for processing a thin film using an energy beam A thin film on a substrate is patterned so as to include an area in which a thin film transistor is to be formed and an area of another patterned thin film or a... |
| US-5,580,800 |
Method of patterning aluminum containing group IIIb Element A thin film transistor according to this invention has a gate electrode comprising a lower layer of aluminum of a high purity of over 99.5% and an upper layer of... |
| US-5,580,799 |
Method of manufacturing transistor with channel implant A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on... |
| US-5,580,798 |
Method of fabricating bipolar transistor having a guard ring In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type... |
| US-5,580,797 |
Method of making SOI Transistor A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the... |
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