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| Patent # | Description |
|---|---|
| US-5,689,474 |
Digital frequency synthesizer There is disclosed a digital frequency synthesizer which converts an ultrnic burst from an echo-ranging sonar system into a continuous signal having a frequency... |
| US-5,689,473 |
Multi-bank synchronous memory system with cascade-type memory cell
structure A synchronous memory system with a cascade-type memory cell structure has memory cells having a cascade type construction (or NAND type configuration), a row... |
| US-5,689,472 |
System and method for providing efficient access to a memory bank Apparatus, method, and system aspects for providing efficient accesses to memory in a computer system, the computer system including a controller, are described.... |
| US-5,689,471 |
Dummy cell for providing a reference voltage in a memory array A dummy cell in a memory array. The memory array includes a storage element for storing one of a first and a second state. The storage element is coupled to... |
| US-5,689,470 |
Semiconductor memory device and method for accessing a memory in the same A semiconductor memory device includes a plurality of memory cells arranged in a matrix, each of which has a gate electrode, a first electrode and a second... |
| US-5,689,469 |
Semiconductor memory devices Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned... |
| US-5,689,468 |
Semiconductor memory device and method for driving the same A semiconductor memory device includes at least one memory block comprising: a plurality of word lines; a plurality of bit lines; and a plurality of memory cells... |
| US-5,689,467 |
Apparatus and method for reducing test time of the data retention
parameter in a dynamic random access memory In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing... |
| US-5,689,466 |
Built in self test (BIST) for multiple RAMs Multiple embedded RAMs are tested, one at a time, for stuck at faults, including multibit faults. Parity for the RAMs is also tested and tests are performed for... |
| US-5,689,465 |
Semiconductor memory device and defective memory cell correction circuit To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating... |
| US-5,689,464 |
Column repair circuit for integrated circuits A column repair circuit for a semiconductor memory having an input/output selection circuit for inputting a control signal, selecting a bit line and a bit bar... |
| US-5,689,463 |
Semiconductor memory device A NAND type EEPROM includes block selecting circuits (BSC1 to BSC6) configured to keep a defective block non-selected in the mode for simultaneous writing and... |
| US-5,689,462 |
Parallel output buffers in memory circuits A memory circuit with programmable memory array organization and number of data output terminals, capable of connecting unused output buffers in parallel in... |
| US-5,689,461 |
Semiconductor memory device having voltage booster circuit coupled to a
bit line charging/equalizing circuit or... An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is... |
| US-5,689,460 |
Semiconductor memory device with a voltage down converter stably
generating an internal down-converted voltage A comparison circuit compares a reference voltage Vref from a reference voltage generation circuit with an internal power supply voltage VCI on an internal power... |
| US-5,689,459 |
Low voltage one transistor flash EEPROM cell using Fowler-Nordheim
programming and erase A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being... |
| US-5,689,458 |
Semiconductor memory device having negative resistance element operated
stably with single low power source A memory cell of an SRAM includes an access transistor, and an MIS switching diode. The access transistor has a drain electrode connected to a bit line of a... |
| US-5,689,457 |
Semiconductor Memory A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines... |
| US-5,689,456 |
Semiconductor non-volatile ferroelectric memory transistor accompanied
with capacitor for increasing potential... A semiconductor non-volatile ferroelectric memory transistor has a lower paraelectric capacitor for creating a conductive channel between a source region and a... |
| US-5,689,455 |
Circuit for programming antifuse bits Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the... |
| US-5,689,454 |
Circuitry and methodology for pulse capture Circuitry and methodology for pulse capture employs S-R latch, precharge, and switch circuitries for quickly sensing and capturing a logic pulse from dynamic... |
| US-5,689,453 |
Data storing apparatus having a memory capable of storing analog data A D/A converter converts input "n" bit digital data into discrete analog data by assigning each of the voltage values V.sub.0 -V.sub.2.spsb.n.sub.-1 to each "n"... |
| US-5,689,452 |
Method and apparatus for performing arithmetic in large galois field
GF(2.sup.n) A method and apparatus for decoding Reed-Solomon codes in large Galois Fields GF(2.sup.n) represents the finite field as a quadratic extension field of one or... |
| US-5,689,451 |
Device for calculating parity bits associated with a sum of two numbers In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two... |
| US-5,689,450 |
Parallel processor A parallel processor for processing a plurality of pieces of data includes a number of unitary processing units provided in parallel equal to the number of... |
| US-5,689,449 |
Decimation filter The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages... |
| US-5,689,447 |
Temperature-compensated, self-calibrating, contact-type gaging system
and method for calibrating the same A temperature-compensated, self-calibrating, contact-type gaging system and method for calibrating the same. The system is configured to run in a calibration... |
| US-5,689,446 |
Foot contour digitizer Apparatus for determining a contour of the underside of a person's foot includes an array of gauge pins supported by a first support structure and disposed in... |
| US-5,689,445 |
Electronic compass and attitude sensing system An electronic heading and attitude sensing subsystem which is fully integrated with the existing hardware of an acoustic Doppler current profiler (ADCP)... |
| US-5,689,444 |
Statistical quality control of wind profiler data The quality of wind profiling radar data is evaluated by comparing the probability density function of the power density of sets of returned samples to an... |
| US-5,689,443 |
Method and apparatus for evaluating scanners The apparatus and method for evaluating images for quality assurance parameters of ultrasound image scanners are described. The apparatus includes a digital... |
| US-5,689,442 |
Event surveillance system A surveillance system operable to capture images and sounds concerning events for storage in a random access data store. A data management functionality is... |
| US-5,689,441 |
Signal processing techniques based upon optical devices A signal processing system processes an input signal in real time. The system includes a light valve array for selectively attenuating light incident thereupon... |
| US-5,689,440 |
Voice compression method and apparatus in a communication system The present invention comprises a method for compressing a plurality of voice signals within a voice communication resource (see FIG. 6) having a given bandwidth... |
| US-5,689,439 |
Switched antenna diversity transmission method and system The present invention is an improved switched antenna diversity transmission system for use with an ARQ error protection protocol. The transmitter of the present... |
| US-5,689,438 |
Audio bit stream generator for high definition television utilizing
personal computer, and control method therefor An audio bit stream generator for an HDTV utilizing a PC, including: a hard disc for storing an HDTV audio data encoded and prepared through computer ... |
| US-5,689,437 |
Video display method and apparatus In a video display method of laying out a plurality of objects in a space, and creating images of the objects in units of frames, thereby displaying a series of... |
| US-5,689,436 |
Apparatus for compressing and decompressing video signal While a image is displayed on a color monitor 44 based on a first digital video signal DRGB1 output from a first A-D converter 52, a second digital video signal... |
| US-5,689,435 |
Systems and methods for automated bracket design A design system for designing brackets for gas turbine engines is described. The system may be implemented with a computer workstation and includes a part model... |
| US-5,689,434 |
Monitoring and control of fluid driven tools A system for monitoring and/or controlling the torque applied by a fluid driven tool for driving threaded fasteners, such as tools driven by either air or oil.... |
| US-5,689,433 |
Method and apparatus for compacting integrated circuits with wire length
minimization A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a... |
| US-5,689,432 |
Integrated circuit design and manufacturing method and an apparatus for
designing an integrated circuit in... A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements... |
| US-5,689,431 |
Golf course yardage and information system A player position determining and course management system for a golf course having a plurality of roving units for use by players in playing the course is... |
| US-5,689,430 |
Internal state determining apparatus An internal state determining apparatus according to the present invention includes at least one inner circuit, means for detecting a change in voltage supplied... |
| US-5,689,429 |
Finger wear detection for production line battery tester A method for detecting wear in a battery tester probe. The method includes providing a battery tester unit having at least one tester finger, generating a tester... |
| US-5,689,428 |
Integrated circuits, transistors, data processing systems, printed
wiring boards, digital computers, smart... An integrated circuit includes conductive elements and a radiation sensitive material interposed between the conductive elements and dosed to different... |
| US-5,689,427 |
Method and apparatus for optimal feedrate control on wire-cutting
electric discharging machine (WEDM) Disclosed is a feedrate controlling method and apparatus for controlling a wire-cutting electric discharging machine (WEDM) to operate at optimal feedrate. In... |
| US-5,689,426 |
Computer-controlled master reproducer for depositing a master
reproduction on a substrate, method for... A computer-controlled master reproducer for depositing a master reproduction on a substrate includes a master source containing in machine-readable format one or... |
| US-5,689,425 |
Color registration system for a printing press A control system is disclosed for controlling misregistration between the colors of an image printed on a web. The system includes an imaging device such as a... |
| US-5,689,424 |
Encoded screen records for international postage meters In a digital postage meter having a housing shell, a display screen mounted in the housing shell, and a removable printhead, a method of transmitting information... |
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