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| Patent # | Description |
|---|---|
| US-5,780,933 |
Substrate for semiconductor device and semiconductor device using the
same A one-sided sealed type semiconductor device comprising a substrate proper for a one-sided resin mold provided on the first main surface thereof with a wiring... |
| US-5,780,932 |
Electricity generating unit having a combined cycle and including a gas
turbine and a steam turbine having a... An electricity generating unit having a combined cycle, and comprising, mounted in succession along a common line of shafts via rigid couplings (28, 29, 31), a... |
| US-5,780,931 |
Surface mounting semiconductor device and semiconductor mounting
component A surface mounting semiconductor device or a mounting component includes a metallic carbonate coating on a mounting surface which may be a plated layer of a... |
| US-5,780,930 |
Method for direct attachment of an on-chip bypass capacitor in an
integrated circuit Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip... |
| US-5,780,929 |
Formation of silicided junctions in deep submicron MOSFETS by defect
enhanced CoSi2 formation Deep submicran mosfets with defect enhanced CoSi2 formation and improved silicided junctions. A silicon wafer having a diffusion window is first precleaned with... |
| US-5,780,928 |
Electronic system having fluid-filled and gas-filled thermal cooling of
its semiconductor devices An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a... |
| US-5,780,927 |
Semiconductor device with long lifetime A semiconductor device includes a heat radiator having a convex portion. A reinforcement plate having a thermal conductivity is soldered on a portion of the... |
| US-5,780,926 |
Multichip package device having a lead frame with stacked patterned
metallization layers and insulation layers A multichip package device includes a lead frame having supporting portions and lead portions for electrically connecting the multichip package with an external... |
| US-5,780,925 |
Lead frame package for electronic devices An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact... |
| US-5,780,924 |
Integrated circuit underfill reservoir A method of packaging an integrated circuit. An integrated circuit is connected to a substrate. A reservoir body is applied to the substrate, and the reservoir... |
| US-5,780,923 |
Modified bus bar with Kapton.TM. tape or insulative material on LOC
packaged part A semiconductor device is formed from a die and a lead frame having one or more bus bars. Portions of the bus bars are overlain with an electrically insulative... |
| US-5,780,922 |
Ultra-low phase noise GE MOSFETs A germanium-based field effect transistor has a passivation layer of aluminum oxide below a germanium channel and aluminum oxide gate oxide layer formed over the... |
| US-5,780,921 |
Bipolar transistor constant voltage source circuit A bipolar transistor constant voltage source circuit includes a first transistor having a collector connected through a first resistor to VCC, an emitter... |
| US-5,780,920 |
Method of forming a resistor and integrated circuitry having a resistor
construction A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the... |
| US-5,780,919 |
Electrically programmable interconnect structure having a PECVD
amorphous silicon element In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between... |
| US-5,780,918 |
Semiconductor integrated circuit device having a programmable adjusting
element in the form of a fuse mounted... An input part of a semiconductor integrated circuit includes a fuse element formed from a metal wiring layer and connected between an input pad and a source line... |
| US-5,780,917 |
Composite controlled semiconductor device and power conversion device
using the same In a composite controlled semiconductor device having an insulated gate, a p type semiconductor region forming no channel is provided between a plurality of p... |
| US-5,780,916 |
Asymmetric contacted metal-semiconductor-metal photodetectors A metal-semiconductor-metal (MSM) photodetector, specifically a new, improved low noise device is disclosed. The disclosed device is a MSM photodiode in which... |
| US-5,780,915 |
Semiconductor device having spiral electrode pattern A semiconductor device having a spiral electrode pattern and fabrication method thereof. The device includes an undoped semiconductor substrate, a first and a... |
| US-5,780,914 |
Contact image sensor whose sensory elements have identical output levels A contact image sensor whose sensory elements have similar output levels is disclosed. The sensor includes: a first region consisting of a plurality of light... |
| US-5,780,913 |
Photoelectric tube using electron beam irradiation diode as anode When light is incident on the photoelectric surface of this electron tube, photoelectrons are emitted. These photoelectrons are accelerated and incident on an... |
| US-5,780,912 |
Asymmetric low power MOS devices Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a... |
| US-5,780,911 |
Thin film transistor and method for fabricating the same A thin film transistor that can have a greater on/off current ratio is disclosed. The thin film transistor includes a substrate, a first gate electrode section... |
| US-5,780,910 |
SRAM with stacked capacitor spaced from gate electrodes In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower... |
| US-5,780,909 |
Semiconductor memory device with a two-layer top gate The present invention provides a semiconductor memory device including (a) a substrate, (b) a first MOS transistor acting as a driver, the first MOS transistor... |
| US-5,780,908 |
Semiconductor apparatus with tungstein nitride Through exposure of the top surface of a tungsten film to plasma of a gas including nitrogen at a temperature of 550.degree. C. or less, a tungsten nitride layer... |
| US-5,780,907 |
Semiconductor device having triple wells A semiconductor device including a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first... |
| US-5,780,906 |
Static memory cell and method of manufacturing a static memory cell A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer... |
| US-5,780,905 |
Asymmetrical, bidirectional triggering ESD structure An ESD protection structure which includes, preferably a single semiconductor chip, a forward SCR for coupling across a source of potential and a reverse SCR for... |
| US-5,780,904 |
Semiconductor integrated circuit device for obtaining extremely small
constant current and timer circuit using... To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first... |
| US-5,780,903 |
Method of fabricating a lightly doped drain thin-film transistor A lightly doped drain thin-film transistor having an inverted staggered structure. The transistor has a glass substrate and a gate formed by a Cr layer on the... |
| US-5,780,902 |
Semiconductor device having LDD structure with pocket on drain side A semiconductor device with an LDD structure type MOS transistor is fabricated by forming a gate electrode on a semiconductor layer of a first conductivity type... |
| US-5,780,901 |
Semiconductor device with side wall conductor film A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor... |
| US-5,780,900 |
Thin film silicon-on-insulator transistor having an improved power
dissipation, a high break down voltage, and... A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first... |
| US-5,780,899 |
Delta doped and counter doped dynamic threshold voltage MOSFET for
ultra-low voltage operation A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt... |
| US-5,780,898 |
Semiconductor device with a vertical field effect transistor and method
of manufacturing the same On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally... |
| US-5,780,897 |
ESD protection clamp for mixed voltage I/O stages using NMOS transistors An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least one pair of... |
| US-5,780,896 |
Semiconductor device having shallow impurity region without
short-circuit between gate electrode and source and... Elevated source and drain regions epitaxially grown on both sides of a gate structure cause a dopant impurity to form an extremely shallow p-n junctions in a... |
| US-5,780,895 |
Forward overvoltage protection circuit for a vertical semiconductor
component A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the... |
| US-5,780,894 |
Nonvolatile semiconductor memory device having stacked-gate type
transistor A nonvolatile semiconductor memory device includes a semiconductor substrate having at least one active region defined between two adjacent element-isolation... |
| US-5,780,893 |
Non-volatile semiconductor memory device including memory transistor
with a composite gate structure A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure... |
| US-5,780,892 |
Flash E.sup.2 PROM cell structure with poly floating and control gates A floating gate E.sup.2 PROM cell is provided with a poly silicon floating gate having a pointed, sloped edge. A poly oxide is disposed on the pointed, sloped... |
| US-5,780,891 |
Nonvolatile floating gate memory with improved interploy dielectric A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric. |
| US-5,780,890 |
Nonvolatile semiconductor memory device and a method of writing data in
the same A nonvolatile semiconductor memory device includes an array of a plurality of memory cells formed in a semiconductor substrate and arranged in a matrix of... |
| US-5,780,889 |
Gate overlap drain source flash structure The presently preferred embodiment of the invention provides a memory structure that eliminates the thick gate associated with the offset of the FAMOS transistor... |
| US-5,780,888 |
Semiconductor device with storage node A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a... |
| US-5,780,887 |
Conductivity modulated MOSFET A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the... |
| US-5,780,886 |
Non-volatile semiconductor memory cell and method for production thereof A non-volatile semiconductor memory cell employing a field effect transistor having a gate of the metal/ferroelectric structure or the ... |
| US-5,780,885 |
Accelerometers using silicon on insulator technology Process for the production of accelerometers using the silicon on insulator method. The process comprises the following stages: a) producing a conductive... |
| US-5,780,884 |
Amplication type solid-state imaging device The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix. Each of... |
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