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| Patent # | Description |
|---|---|
| US-5,781,505 |
System and method for locating a trajectory and a source of a projectile A projectile trajectory and source location system and method identifies, calizes, and displays a projectile trajectory relative to one or more stationary... |
| US-5,781,504 |
Shallow water beamforming methodology for toroidal volume search sonar An apparatus and method for beamforming for a toroidal volume search sonar. onar array vehicle motion is used to reduce reverberation by fixing beams ... |
| US-5,781,503 |
Method for attenuating surface wavetrains in seismic data A method for attenuating source-generated surface wavetrains in a set of seismic data traces. According to the method, the seismic data traces are Fourier... |
| US-5,781,502 |
Method and device for filtering elliptical waves propagating in a medium The present invention relates to a filtering method for discriminating elliptical waves among other waves propagating in a material medium (such as a geologic... |
| US-5,781,501 |
Circuit and method for securing write recovery operation in a
synchronous semiconductor memory device A circuit and a method for securing a write recovery operation in a semiconductor memory device. The write recovery security circuit comprises an external signal... |
| US-5,781,500 |
Method and circuit for generating internal pulse signals in synchronous
memory A method and a circuit for generating internal pulse signals in a synchronous memory is provided. A first pulse signal is generated in response to a burst mode... |
| US-5,781,499 |
Semiconductor memory device The semiconductor memory device of the present invention is provided with at least: a first sync-signal generation circuit that generates and outputs a first... |
| US-5,781,498 |
Sub word line driving circuit and a semiconductor memory device using
the same A sub word line driving circuit for driving a sub word line is used for a semiconductor memory device having a hierarchical word line structure. The sub word... |
| US-5,781,497 |
Random access memory word line select circuit having rapid dynamic
deselect A word line select circuit (10) having a rapid de-select operation is disclosed. A group of word lines (12a-12d) is selected in response to a row address and the... |
| US-5,781,496 |
Block write power reduction memory with reduced power consumption during
block write mode A video memory device has a normal write mode and a block write mode, and includes a global write driver driving global input/output (I/O) lines, and a number of... |
| US-5,781,495 |
Semiconductor memory device for multi-bit or multi-bank architectures In a semiconductor memory device, global column-select lines are provided for selecting specific memory-cell arrays in accordance with select signals, and a pair... |
| US-5,781,494 |
Voltage pumping circuit for semiconductor memory device A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an... |
| US-5,781,493 |
Semiconductor memory device having block write function A semiconductor memory device is provided with a first data line pair, second data line pair, a plurality of first bit line pairs respectively connected to the... |
| US-5,781,492 |
System and method for mapping memory to DRAM after system boot from
non-volatile memory A computer system is presented having a mechanism for re-mapping memory address space after system initiation. The mechanism includes a microcontroller embodying... |
| US-5,781,491 |
Memory device having divided cell array blocks to which different
voltage levels are applied Disclosed is a semiconductor memory device capable of reducing power consumption. The semiconductor memory device according to the present invention divides a... |
| US-5,781,490 |
Multiple staged power up of integrated circuit A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS... |
| US-5,781,489 |
Semiconductor storage device The invention provides a semiconductor storage device which realizes such reliability that a current characteristic does not exhibit a variation even after use... |
| US-5,781,488 |
DRAM with new I/O data path configuration In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay... |
| US-5,781,487 |
Bit line selection circuit An improved bit line selection circuit which is capable of preventing power consumption of Vpp by delaying an external signal for a predetermined time, first... |
| US-5,781,486 |
Apparatus for testing redundant elements in a packaged semiconductor
memory device During compression mode testing of a semiconductor memory device, a memory address is compressed to free up 2 or more bits in the address (e.g., an 11-bit... |
| US-5,781,485 |
Apparatus and method for controlling operating mode in semiconductor
memory device An apparatus and method for controlling an operating mode in a semiconductor memory device is provided. During test mode, test mode selection signals are... |
| US-5,781,484 |
Semiconductor memory device Normal column selection signal switching device (20) is provided to switch a signal outputted from normal column selection signal generating device (19) in... |
| US-5,781,483 |
Device and method for repairing a memory array by storing each bit in
multiple memory cells in the array A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric... |
| US-5,781,482 |
Semiconductor memory device A semiconductor memory having a function that set/reset information is directly written into each of the memory cells is disclosed. The semiconductor memory... |
| US-5,781,481 |
Semiconductor memory device with reduced leakage current and improved
data retention A semiconductor memory device has memory cells in which data are represented by a first voltage level and a second voltage level higher than the first voltage... |
| US-5,781,480 |
Pipelined dual port integrated circuit memory A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is... |
| US-5,781,479 |
Memory device A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for... |
| US-5,781,478 |
Nonvolatile semiconductor memory device There is provided a non-volatile semiconductor memory device comprising: a memory cell array in which a plurality of memory cell units are arranged in a matrix... |
| US-5,781,477 |
Flash memory system having fast erase operation A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with... |
| US-5,781,476 |
Nonvolatile semiconductor memory device Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit... |
| US-5,781,475 |
Simplified page mode programming circuit for EEPROM requiring only one
high voltage line for selecting bit lines An apparatus for page mode programming of an EEPROM cell array applications is described. The apparatus comprises a control gate potential control means and a... |
| US-5,781,474 |
Parallel programming method of memory words and corresponding circuit A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of... |
| US-5,781,473 |
Variable stage charge pump A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A... |
| US-5,781,472 |
Bit map addressing schemes for flash/memory Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output"... |
| US-5,781,471 |
PMOS non-volatile latch for storage of redundancy addresses A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The... |
| US-5,781,470 |
Protected writing method for an integrated memory circuit and a
corresponding integrated circuit The present invention concerns a method for protecting a write operation of a memory cell within an integrated circuit that comprises the introduction of a... |
| US-5,781,469 |
Bitline load and precharge structure for an SRAM memory An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its... |
| US-5,781,468 |
Semiconductor memory device comprising two kinds of memory cells
operating in different access speeds and... A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs... |
| US-5,781,467 |
Decoding method for ROM matrix having a silicon controlled rectifier
structure A decoding method is used for a ROM matrix having silicon controlled rectifier memory units. In the memory units a voltage is applied to the emitter terminal and... |
| US-5,781,466 |
Semiconductor memory with built-in cache A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can... |
| US-5,781,465 |
Method and apparatus for fast carry generation detection and comparison Two binary two's complement numbers X and Y are compared using half-adders and a parallel prefix-and circuit to find a carry bit that results from forming the... |
| US-5,781,464 |
Apparatus and method for incrementing floating-point numbers represented
in diffrent precision modes An incrementer for performing floating-point calculations is capable of incrementing a floating-point number represented in one of several different precision... |
| US-5,781,463 |
Adaptive digital filter with high speed and high precision coefficient
sequence generation An adaptive digital filter includes a finite impulse response digital filter for performing a convolution calculation by multiplying a code sequence with a... |
| US-5,781,462 |
Multiplier circuitry with improved storage and transfer of booth control
coefficients It is an object of the present invention to simplify a multiplier so as to reduce the circuit scale of a digital filter which uses a large number of multipliers.... |
| US-5,781,461 |
Digital signal processing system and method for generating musical
legato using multitap delay line with crossfader A sampled data, delay line structure that includes a sampled data delay line, two readers for reading data at corresponding positions of the delay line,... |
| US-5,781,460 |
System and method for chaotic signal identification A chaotic signal processing system receives an input signal provided by a nsor in a chaotic environment and performs a processing operation in connection... |
| US-5,781,459 |
Method and system for rational frequency synthesis using a numerically
controlled oscillator A numerically controlled oscillator (11), (NCO), generates an NCO output (114) having a time-averaged frequency proportional to a rational number, even if the... |
| US-5,781,458 |
Method and apparatus for generating truly random numbers A method and apparatus for generating truly random numbers which may be used in a cryptographic key generator is adapted to extract entropy from the output... |
| US-5,781,457 |
Merge/mask, rotate/shift, and boolean operations from two instruction
sets executed in a vectored mux on a dual-ALU A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the... |
| US-5,781,456 |
Software select and test A software-controlled select and test system for use with a spacecraft. The system reduces the assembly, integration, test time and improves performance of the... |
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