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| Patent # | Description |
|---|---|
| US-5,790,472 |
Adaptive control of marine seismic streamers A method for controlling the position and shape of marine seismic streamer cables, whereby a plurality of real time signals from a marine seismic data... |
| US-5,790,471 |
Water/sediment interface monitoring system using frequency-molulated
continuous wave The water/sediment interface in a body of water near bridge piers and simr structures exposed to scour, is sensed and transformed by a frequency-modulated... |
| US-5,790,470 |
Decoder circuit having a predecoder acitivated by a reset signal A decoder circuit prevented from multi-selection is disclosed. The decoder circuit has a pulse generator receiving an external clock signal and outputting a... |
| US-5,790,469 |
Programmable voltage supply circuitry Internal programmable voltage supply circuitry is provided for a programmable transistor integrated circuit device, such as a programmable logic device or a... |
| US-5,790,468 |
Refresh counter for synchronous dynamic random access memory and method
of testing the same A refresh counter for an SDRAM and a method of testing the same. An internal bank select address for the test of the refresh counter has a predetermined state in... |
| US-5,790,467 |
Apparatus and method for a direct-sense sense amplifier with a single
read/write control line In a dynamic random access memory, the sense amplifiers associated with the storage cells have the direct sense circuitry (MNEW, MNWE.sub.--, MNRD, MNRD.sub.--)... |
| US-5,790,466 |
Multiple precharging semiconductor memory device The semiconductor memory device of this invention includes a plurality of bit lines for carrying data read out from memory cells and supplying the data to a... |
| US-5,790,465 |
Wafer burn-in test circuit and a method thereof A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of... |
| US-5,790,464 |
Method for arranging a memory cell array in semiconductor memory device A method of arranging a memory cell array in a semiconductor memory device, comprising the steps of dividing the memory cell array into a plurality of memory... |
| US-5,790,463 |
On-chip mobile ion contamination test circuit A circuit for testing for mobile ion contamination of a semiconductor chip has an enabling circuit, a voltage pump, and a regulating circuit. In a normal... |
| US-5,790,462 |
Redundancy control An integrated circuit memory structure is disclosed where the read and write buses (true and complement) are coupled to redundant input/output select circuits... |
| US-5,790,461 |
Register file with bypass capability Control circuitry for a register file is provided which allows immediate or rapid output of input write data by bypassing the need to store the data and then... |
| US-5,790,460 |
Method of erasing a flash EEPROM memory The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one... |
| US-5,790,459 |
Memory circuit for performing threshold voltage tests on cells of a
memory array An integrated memory circuit having an array of memory cells and which is operable in at least one test mode as well as in a normal operating mode, and a true... |
| US-5,790,458 |
Sense amplifier for nonvolatile semiconductor memory device A sense amplifier for transferring data between a data input/output line and a bit line in a nonvolatile semiconductor memory device includes two isolated... |
| US-5,790,457 |
Nonvolatile integrated circuit memory devices having ground interconnect
lattices with reduced lateral dimensions Nonvolatile integrated circuit memory devices having ground interconnect lattices are provided to have reduced lateral dimensions because the ground interconnect... |
| US-5,790,456 |
Multiple bits-per-cell flash EEPROM memory cells with wide program and
erase V.sub.t window There is provided an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR... |
| US-5,790,455 |
Low voltage single supply CMOS electrically erasable read-only memory P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells... |
| US-5,790,454 |
Data sensing apparatus and method of multi-bit memory cell A data sensing apparatus and method of a multi-bit memory cell includes a first step of generating 2.sup.m -1 different reference voltages, a second step of... |
| US-5,790,453 |
Apparatus and method for reading state of multistate non-volatile memory
cells An apparatus determining the state of a multistate memory cell. The apparatus includes three sense amplifiers, each with an associated reference cell which... |
| US-5,790,452 |
Memory cell having asymmetrical source/drain pass transistors and method
for operating same A memory cell having an asymmetrical transistor which provides access to a data storage circuit of the memory cell. The asymmetrical transistor exhibits a... |
| US-5,790,451 |
Memory cell, memory device and method of fabricating the same A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or... |
| US-5,790,450 |
Semiconductor memory device having bit lines widely spaced without
sacrifice of narrow pitch of source/drain... When a data bit is read out from a semiconductor read only memory device, a current-mirror type sense amplifier is electrically connected through a bit line, a... |
| US-5,790,449 |
Method of driving optical modulation device A liquid crystal apparatus includes a liquid crystal device having a group of scanning electrodes and a group of signal electrodes intersecting each other to... |
| US-5,790,448 |
On-chip program voltage generator for antifuse repair A memory chip having an on-chip high voltage generator and charge pump. |
| US-5,790,447 |
High-memory capacity DIMM with data and state memory A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data... |
| US-5,790,446 |
Floating point multiplier with reduced critical paths using delay
matching techniques A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors... |
| US-5,790,445 |
Method and system for performing a high speed floating point add
operation A system and method for calculating a floating point add/subtract of a plurality of floating point operands is disclosed. The system comprises at least one pair... |
| US-5,790,444 |
Fast alignment unit for multiply-add floating point unit A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B... |
| US-5,790,443 |
Mixed-modulo address generation using shadow segment registers A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously... |
| US-5,790,442 |
Method and apparatus for generating low-discrepancy sequence, as well as
apparatus and method for calculating... A method and system are provided for generating a low-discrepancy sequence at high speed, comprising means for expanding an i-th coordinate value u.sub.n.sup.(i)... |
| US-5,790,441 |
Lossless transform coding system for digital signals The invention provides a reversible eight-element discrete cosine transform system which can be realized with a practical circuit and provide transform values... |
| US-5,790,440 |
Apparatus for estimating filter coefficients An apparatus for estimating filter coefficients operates in a system which includes a filter simulating characteristics of an unknown signal transmission system... |
| US-5,790,439 |
Reduced test time finite impulse response digital filter A k-bit data input and a 1-bit scan input of a scan flip-flop (21.sub.i) of a multiply-accumulation operation unit (4.sub.i) respectively receive a k-bit data... |
| US-5,790,438 |
Radio navigation testing method and device using standard signal
measuring and generating equipment For the testing of radio navigation instruments by means of an automatic testing system controlling electric signal measuring and generating equipment, said... |
| US-5,790,437 |
Graphical interface for programming ramping controllers An interface for graphically programming a ramping controller coupled to and controlling an electric heater is implemented with a microcomputer. The interface... |
| US-5,790,436 |
Realistic worst-case circuit simulation system and method A system and method of simulating operation of an integrated circuit. First, circuit characteristics of circuit components are measured, and a set of circuit... |
| US-5,790,435 |
Automated development of timing diagrams for electrical circuits A computer-implemented method and apparatus that automates the entry, modification, and verification of timing diagrams for electrical circuits. The... |
| US-5,790,434 |
Hybrid method of Characterizing spatial aspects of the transect of a
river having predetermined water surface... Profiles of a river area analyzed by determining a ruler length characterizing the size of topological features of the river. The perimeter of a transect of the... |
| US-5,790,433 |
Method for controlling laser power in a texturing process A disk texturing tool is used, for example, to provide textured spots in an annular portion of both sides of a disk for a hard disk drive. Disks are moved into... |
| US-5,790,432 |
Universal measuring instrument with signal processing algorithm
encapsulated into interchangeable intelligent... A meter (10) is capable of use with a plurality of different sensor heads (16, 16b). The reading meter (12) includes a digital display (20), a processor (22) and... |
| US-5,790,431 |
Method and system for measuring availability in a distributed network A method and apparatus for determining the availability of a workstation in a distributed network. Availability is determined using an Availability Measurement... |
| US-5,790,430 |
Variable speed fan failure detector The failure of a motor to maintain a commanded speed is detected by the disclosed variable speed fan failure detector. The commanded speed varies as a function... |
| US-5,790,429 |
Mail coding system A system for processing and encoding mail including a bin configured to hold mail and a transport coupled to said bin to receive mail therefrom. The transport... |
| US-5,790,428 |
Device to measure and provide data for plant population and spacing
variability An apparatus and method for determining plant population, plant spacing, plant spacing variability, and other information regarding row-planted crops. The... |
| US-5,790,427 |
Event history data acquisition An event data recorder and method for recording data relating to a distinct event which pertains to operation of a mechanism. The recorder comprises a device for... |
| US-5,790,426 |
Automated collaborative filtering system An automated collaborative filtering (ACF) system for recommending at least one item to a first user based on similarity in preference of the user as compared... |
| US-5,790,425 |
Generic server benchmarking framework in a client-server environment A computer implemented framework method for server benchmarking in a client server environment including a server and at least one client system is provided. The... |
| US-5,790,424 |
Plant monitoring apparatus and monitoring method In a display method and a display unit, information which is required or often used by an operator is processed visually conspicuously by enlarged display or... |
| US-5,790,423 |
Interactive audio transmission receiving and playback system The present invention includes a system for transmitting, receiving, storing and replaying a user selected program, which has a service center including an... |
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