Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-5,790,877 |
Method for controlling a processor for power-saving in a computer for
executing a program, compiler medium and... In a processor system including a plurality of hardware resources, a method for arranging a program to suppress the power consumption by the resources includes... |
| US-5,790,876 |
Power saving control system and method for use with serially connected
electronic devices A system including a plurality of electronic devices connected together through a bus, which can realize reduction in power consumption while ensuring... |
| US-5,790,875 |
Method for lowering power consumption in a computing device The method relates to minimizing power consumption in a computing device, which executes the requested tasks in a high power mode, in which it has normal... |
| US-5,790,874 |
Information processing apparatus for reducing power consumption by
minimizing hamming distance between... An instruction sequence optimization apparatus optimizes programs used in an information processing system that includes a program memory for storing programs,... |
| US-5,790,873 |
Method and apparatus for power supply switching with logic integrity
protection A method and apparatus for providing power management functions in a computer or other electronic system which includes a primary power supply, a trickle power... |
| US-5,790,872 |
Interrupt control handler for a RISC-type microprocessor The present invention relates to a data processing device that can perform independently a debug interruption process and a program interruption process. The... |
| US-5,790,871 |
System and method for testing and debugging a multiprocessing interrupt
controller A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit... |
| US-5,790,870 |
Bus error handler for PERR# and SERR# on dual PCI bus system An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR#... |
| US-5,790,869 |
Circuit for selectively preventing a microprocessor from posting write
cycles An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by... |
| US-5,790,868 |
Customer information control system and method with transaction
serialization control functions in a loosely... A distributed computer system having a plurality of end user terminals and a plurality of loosely coupled server computers that share no resources with each... |
| US-5,790,867 |
Compiler with extended redundant copy elimination A compiler and method of compiling provide extended redundant copy elimination by eliminating copy statements having provably equivalent data items when it is... |
| US-5,790,866 |
Method of analyzing definitions and uses in programs with pointers and
aggregates in an optimizing compiler A method for analyzing and optimizing programs that contain pointers and/or aggregates, such as found in the languages C, C++, FORTRAN-90, and Ada. The method... |
| US-5,790,865 |
Method and apparatus for reordering components of computer programs A method and system for reordering sections of a computer program are disclosed. The computer program is executed during an experimental execution period. During... |
| US-5,790,863 |
Method and system for generating and displaying a computer program A method and system for generating a computer program. In a preferred embodiment, the present invention provides a program tree editor for directly manipulating... |
| US-5,790,862 |
Resource assigning apparatus which assigns the variable in a program to
resources A resource assigning apparatus which generates assignments which are combinations of variables and their respective live ranges, which investigates, for each... |
| US-5,790,861 |
Method and apparatus for generating executable code from object-oriented
C++ source code The present invention provides an improved method and apparatus for generating executable computer code for an application program written in C++ source code. In... |
| US-5,790,860 |
Method and apparatus for patching code residing on a read only memory
device A method and apparatus for generating patching resources in an information processing system having operating instructions on a Read Only Memory Device. The... |
| US-5,790,859 |
Method of, system for, and computer program product for efficient
identification of private variables in... Privatization or identification of private variables in single-entry strongly connected regions or program loops by the use of dummy identity assignment... |
| US-5,790,858 |
Method and system for selecting instrumentation points in a computer
program The present invention provides a method in a computer system for selecting instrumentation points in a computer program. Instrumentation points are locations... |
| US-5,790,857 |
Method for associating and storing arbitrary data with graphical user
interface elements Data structure and methods associating an arbitrary list of properties with user interface items on a graphical user interface display. Each property has a tag... |
| US-5,790,856 |
Methods, apparatus, and data structures for data driven computer patches
and static analysis of same The present invention teaches a variety of methods, apparatus and data structures for providing data driven patching. According to one embodiment, patches are... |
| US-5,790,855 |
System, method and article of manufacture for type checking
appropriateness of port connection and variable... Method, system and article of manufacture for connecting multiport object oriented components for use in an object oriented based applet or application. The... |
| US-5,790,854 |
Efficient stack utilization for compiling and executing nested if-else
constructs in a vector data processing... A computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors (10). A vector bit... |
| US-5,790,853 |
Workspace management apparatus A workspace management section collects resources related to a job and manages them as a workspace separately from resource management of a primary resource... |
| US-5,790,852 |
Computer with extended virtual storage concept In a computer including an operating system comprising a virtual storage organization concept providing storage space for parallel program execution in... |
| US-5,790,851 |
Method of sequencing lock call requests to an O/S to avoid spinlock
contention within a multi-processor environment An arbitration procedure allowing processes and their associated processors to perform useful work while they have pending service requests for access to shared... |
| US-5,790,850 |
Fault resilient booting for multiprocessor computer systems A multiprocessor computer system determines that the hard reset designated BSP has failed by examining its status bits. The designated BSP then selects a... |
| US-5,790,849 |
Method and apparatus to permit the boot of a shared memory buffer
architecture employing an arbitrary operating... A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge,... |
| US-5,790,848 |
Method and apparatus for data access and update in a shared file
environment A distributed storage system provides a method and apparatus for storing, retrieving, and sharing data items across multiple physical storage devices that may... |
| US-5,790,847 |
Integration of groupware with activity based management via facilitated
work sessions A network application for automatically formatting and printing documents to be used as product planning manuals organizational personnel in determining product... |
| US-5,790,846 |
Interrupt vectoring for instruction address breakpoint facility in
computer systems An exception handler for a computer system, particularly for performance monitoring facilities, employs implementation-dependent steps executed from a kernel... |
| US-5,790,845 |
System with reservation instruction execution to store branch target
address for use upon reaching the branch point To improve the efficiency of instruction branch operations, particularly in a pipeline processor, a branch reservation instruction is generated during program... |
| US-5,790,844 |
Millicode load and test access instruction that blocks interrupts in
response to access exceptions A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current... |
| US-5,790,843 |
System for modifying microprocessor operations independently of the
execution unit upon detection of... Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize... |
| US-5,790,842 |
Processing system with simultaneous utilization of multiple clock signals A method and apparatus for use in a set top box processing system to permit simultaneous utilization of two system clocks in applications in which certain... |
| US-5,790,841 |
Method for placement of clock buffers in a clock distribution system A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row... |
| US-5,790,840 |
Timestamp systems, methods and computer program products for data
processing system Timestamp updating systems, methods and computer program products for data processing systems provide a timestamp register that stores a current value of a... |
| US-5,790,839 |
System integration of DRAM macros and logic cores in a single chip
architecture A chip architecture standard merges dynamic random access memory (DRAM) macros and logic cores. The standard from merged DRAM and logic design provides the... |
| US-5,790,838 |
Pipelined memory interface and method for using the same According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended... |
| US-5,790,837 |
Method and system for device virtualization based on an interrupt
request in a dos-based environment A technique for providing device virtualization in an MS-DOS based operating environment, using an interrupt request (e.g., a non-maskable interrupt), is... |
| US-5,790,836 |
Apparatus for simulating digital signal processing circuits Test vector storing means outputs data for simulation at a predetermined transfer speed. A signal processor executes the simulation of a digital signal... |
| US-5,790,835 |
Practical distributed transmission line analysis A system and method is provided for that allows the introduction of small sections of idealized conductive elements to be placed along a transmission line. The... |
| US-5,790,834 |
Apparatus and method using an ID instruction to identify a computer
microprocessor An identification apparatus and method for identifying the microprocessor, including a read-only memory for storing microprocessor ID data having data fields for... |
| US-5,790,833 |
Integrated circuit, having microprocessor and telephony peripheral
circuitry, having capability of being placed... An in-circuit emulation capability mode incorporated in an integrated circuit. The in-circuit emulation capability mode disables the microcontroller of the... |
| US-5,790,832 |
Method and apparatus for tracing any node of an emulation A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically... |
| US-5,790,831 |
VL-bus/PCI-bus bridge A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV#... |
| US-5,790,830 |
Extracting accurate and efficient timing models of latch-based designs A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst... |
| US-5,790,829 |
Event synchronization mechanism A computer process determines that processing by a resource manager of all previously sent event structures has been completed by sending a tag event structure... |
| US-5,790,828 |
Disk meshing and flexible storage mapping with enhanced flexible caching A data processing system which includes a processor having a processor memory and a mechanism for specifying an address that corresponds to a processor-requested... |
| US-5,790,827 |
Method for dependency checking using a scoreboard for a pair of register
sets having different precisions A dependency checking method includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each... |
Copyright 2008−2012 Patents.com
