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| Patent # | Description |
|---|---|
| US-5,869,902 |
Semiconductor device and manufacturing method thereof A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an... |
| US-5,869,901 |
Semiconductor device having aluminum interconnection and method of
manufacturing the same A semiconductor device and a method of manufacturing the same are provided which comprises a metal interconnection consisting of a titanium-aluminum film with... |
| US-5,869,900 |
Sea-of-cells array of transistors The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local... |
| US-5,869,899 |
High density interconnect substrate and method of manufacturing same A method of creating high density interlayer interconnects on circuit carrying substrates. A circuit pattern (20) is formed on one side of a substrate (10), and... |
| US-5,869,898 |
Lead-frame having interdigitated signal and ground leads with high
frequency leads positioned adjacent a corner... A lead-frame is sealed in a full-mold insulating package together with a semiconductor chip; the lead-frame has a conductive die pad for mounting the... |
| US-5,869,897 |
Mounting arrangement for securing an intergrated circuit package to heat
sink A top surface of a protective cover of an IC component package is provided with a centered-protrusion, e.g., such as a cylindrical peg, that extends above the... |
| US-5,869,896 |
Packaged electronic module and integral sensor array An electronic module includes multiple stacked bare IC chips ("a stack") and a sensor assembly that is mechanically coupled to an end surface of the stack.... |
| US-5,869,895 |
Embedded memory assembly Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn,... |
| US-5,869,894 |
RF IC package The specification describes a MCM IC package with improved RF grounding. The package has at least one RF IC chip bonded to an interconnect substrate and the... |
| US-5,869,893 |
Semiconductor device having a trapezoidal joint chip A semiconductor device comprises at least two semiconductor elements connected together at a connecting region of the semiconductor elements. At least one joint... |
| US-5,869,892 |
Noise eliminating element and electrical circuit having the same Disclosed are a noise eliminating element having a junction of components of two kinds of electroconductive materials, characterized in that the absolute values... |
| US-5,869,891 |
Powdered metal heat sink with increased surface area A method and apparatus for dissipating heat from a semiconductor device. A heat sink embodying the method includes an exterior surface contoured to better... |
| US-5,869,890 |
Insulation substrate for a semiconductor device A Ceramic Bonding Copper (CBC) substrate used in semiconductor modules includes a ceramic plate having foil-shaped copper plates bonded to the ceramic plate by... |
| US-5,869,889 |
Thin power tape ball grid array package An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape... |
| US-5,869,888 |
Semiconductor device with lead structure on principal surface of chip A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to... |
| US-5,869,887 |
Semiconductor package fabricated by using automated bonding tape A transparent base film of a semiconductor device package has a device hole into which a semiconductor chip is inserted. Formed on the base film are a plurality... |
| US-5,869,886 |
Flip chip semiconductor mounting structure with electrically conductive
resin A semiconductor chip is flip chip bonded on a substrate wherein the semiconductor chip has a first surface on which bumps are provided. An insulating sealing... |
| US-5,869,884 |
Semiconductor device having lead terminal on only one side of a package A semiconductor device of the present invention in which a plurality of lead terminals are provided for only one side, comprising a plurality of leads connected... |
| US-5,869,883 |
Packaging of semiconductor circuit in pre-molded plastic package An inexpensive pre-molded package for electronic semiconductor circuit with increased thermal extraction capability, improved electrical performance, improved... |
| US-5,869,882 |
Zener diode structure with high reverse breakdown voltage A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity... |
| US-5,869,881 |
Pillar bipolar transistor The present invention relates to a pillar bipolar transistor and the fabricating method thereof, the active region on which the emitter region, the base region... |
| US-5,869,880 |
Structure and fabrication method for stackable, air-gap-containing low
epsilon dielectric layers A structured dielectric layer and fabrication process for separating wiring levels and wires within a level on a semiconductor chip is described incorporating a... |
| US-5,869,879 |
CMOS integrated circuit having a sacrificial metal spacer for producing
graded NMOS source/drain junctions... An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD... |
| US-5,869,878 |
Semiconductor device with temperature detecting diode, method of forming
the device and temperature detecting... The object of the present invention is to provide a temperature detecting method wherein a temperature detecting diode is formed in the proximity of and... |
| US-5,869,877 |
Methods and apparatus for detecting pattern dependent charging on a
workpiece in a plasma processing system A charge monitoring apparatus measures an electrical charge deposited on a multiple-layered workpiece, such as a semiconductor wafer, in a plasma processing... |
| US-5,869,876 |
Semiconductor strain sensor A semiconductor strain sensor has a gauge forming region on a p-type substrate surrounded by a p-type isolation region that reaches the p-type substrate. The... |
| US-5,869,875 |
Lateral diffused MOS transistor with trench source contact A lateral diffused MOS transistor formed in a doped epitaxial semiconductor layer on a doped semiconductor substrate includes a source contact to the substrate... |
| US-5,869,874 |
Field effect transistor with barrier layer A field effect transistor includes, a silicon substrate having impurity doping of a first conductivity type; source and drain diffusion regions of a second... |
| US-5,869,873 |
Electrostatic discharge protection circuit having eprom An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic... |
| US-5,869,872 |
Semiconductor integrated circuit device and manufacturing method for the
same A semiconductor integrated circuit device having an SOI structure is capable of preventing occurrence of leak current flowing from a diffusion layer even when a... |
| US-5,869,871 |
Semiconductor device capable of avoiding damage by ESD In a semiconductor device including a semiconductor substrate, first and second external terminals, a first impurity diffusion region connected to the first... |
| US-5,869,870 |
Electrostatic discharge (ESD) protective device for integrated circuit
packages with no-connect pins An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the... |
| US-5,869,869 |
Microelectronic device with thin film electrostatic discharge protection
structure Microelectronic devices are formed on a substrate of an integrated circuit. An electrically conductive ground or power plane, and an ElectroStatic Discharge... |
| US-5,869,868 |
SOI trench DRAM cell for 256 MB DRAM and beyond A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the... |
| US-5,869,867 |
FET semiconductor integrated circuit device having a planar element
structure In a semiconductor device, an extra wiring area generated by the connection of an upper layer wiring to an element on a semiconductor substrate is reduced to... |
| US-5,869,866 |
Integrated circuit having sacrificial spacers for producing graded NMOS
source/drain junctions possibly... An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD... |
| US-5,869,865 |
Lateral field effect transistor with minimum total on-resistance In a rectangular lateral field effect transistor including a rectangular active region formed within a semiconductor substrate, and at least one rectangular... |
| US-5,869,864 |
Field effect controlled semiconductor component A semiconductor component having a body with an upper surface, a base zone having a portion adjoining the upper surface of the semiconductor body, at least one... |
| US-5,869,863 |
memory having a trench type gate structure A read-only memory (ROM) and method for manufacturing a ROM having trench-type gate regions and source/drain regions, wherein the trench-type gate regions are... |
| US-5,869,862 |
High integration semiconductor device Control gate electrodes 12 are formed on field oxidation layers 19. Anisotropic etching is carried out by covering all the regions except for a source region by... |
| US-5,869,861 |
Coaxial capacitor for DRAM memory cell A DRAM capacitor is formed over a device with FOX regions and device areas with S/D regions. Form a planarization silicon oxide layer over the device and FOX... |
| US-5,869,860 |
Ferroelectric memory device and method for producing the device A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor... |
| US-5,869,859 |
DRAM capacitor having lower electrode and dielectric layer of same
planar shape preformed on field DRAM oxide film In a DRAM memory cell built in a semiconductor device, a capacitor is formed on a field oxide film so as not to superpose upon a transistor. An area of the field... |
| US-5,869,858 |
Semiconductor device for reducing variations in characteristics of the
device A semiconductor device comprises a substrate, a first conductive layer formed on the substrate and comprising a first layer and a second layer formed on the... |
| US-5,869,857 |
CMOS photodetectors with wide range operating region A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the... |
| US-5,869,856 |
Field effect transistor Disclosed is a field effect transistor which has: an operating layer which is of a compound semiconductor; a first conductive layer which is formed as a channel... |
| US-5,869,855 |
Charge-coupled device with photo chromic layer A charge-coupled device including, a light-receiving part having a glass and receiving an image, a photo chromic layer formed on the glass and being... |
| US-5,869,854 |
Solid-state imaging device and method of manufacturing the same A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed... |
| US-5,869,853 |
Linear charge-coupled device having improved charge transferring
characteristics A linear CCD (charge-coupled device) including: a photodiode-array having a plurality of photodiodes for converting incident light plural charges, respectively;... |
| US-5,869,852 |
Semiconductor integrated circuit and semiconductor integrated circuit
having layout designed by cell base system A semiconductor integrated circuit including a second electrode on a dielectric film opposite a first electrode and constituting a capacitor. Grounding wiring is... |
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