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| Patent # | Description |
|---|---|
| US-5,870,617 |
Systems, circuits and methods for mixed voltages and programmable
voltage rails on integrated circuits An integrated circuit (110) includes, on a single chip, distinct supply voltage terminals and internal on-chip supply conductors connected respectively thereto,... |
| US-5,870,616 |
System and method for reducing power consumption in an electronic circuit While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer... |
| US-5,870,615 |
Automatic cellular phone battery charging by mobile personal computer
using configuration write data and... A PCMCIA card having cellular phone battery charging circuitry, and an adapter cable having a PCMCIA card connector equipped with a battery characteristic... |
| US-5,870,614 |
Thermostat controls dsp's temperature by effectuating the dsp switching
between tasks of different... A data processor chip has a sensor that senses the temperature of the substrate. When the sensor senses that the temperature has increased beyond a predetermined... |
| US-5,870,613 |
Power mangement system for a computer A power management system for a personal computer comprises a power management processor, a switchable power supply and a keep alive power supply. The processor... |
| US-5,870,612 |
Method and apparatus for condensed history buffer The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions,... |
| US-5,870,611 |
Install plan object for network installation of application programs An installation plan object is built for installing an application in a network. The empty installation plan object is first created from a template of a... |
| US-5,870,610 |
Autoconfigurable method and system having automated downloading A method of upgrading a system, such as a computer, that supports a variety of devices includes locating and identifying a first supported device and determining... |
| US-5,870,609 |
Technique for bootstrapping executable code to an adapter A method of bootstrapping executable code to a microprocessor controller from a personal computer (PC) via a bidirectional interface, e.g., a standard PC... |
| US-5,870,608 |
Method and apparatus for displaying text including context sensitive
information derived from parse tree A method and apparatus for displaying text which efficiently couples information derived from the parse tree for the text with the display of the text. Use of... |
| US-5,870,607 |
Method and apparatus for selective replay of computer programs A user can selectively replay portions of a computer program execution, so that the entire program need not be run again to support further test and debug. A... |
| US-5,870,606 |
Data triggered trace technique for debugging software programs A technique for permitting tracepoints to be set relative to data elements for the debugging of a procedural program is disclosed. A proxy object is provided for... |
| US-5,870,605 |
Middleware for enterprise information distribution A method and apparatus for publishing and receiving events to and from a network. A plurality of "publisher" entities publish information and a plurality of... |
| US-5,870,604 |
Job execution processor changing method and system, for load
distribution among processors In a system including a plurality of processors for executing jobs, an execution processor of which the number of jobs waiting for execution is large is changed... |
| US-5,870,603 |
Method and system for storing exponent codes in a multi-processor
computer to produce putputs according to an... A method and system utilized by a multi-processor computer for storing exponent codes is provided. The multi-processor computer includes a plurality of... |
| US-5,870,602 |
Multi-processor system with system wide reset and partial system reset
capabilities A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache... |
| US-5,870,601 |
Data processing apparatus and method for correcting faulty microcode in
a ROM device via a flag... The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only... |
| US-5,870,599 |
Computer system employing streaming buffer for instruction preetching Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for... |
| US-5,870,598 |
Method and apparatus for providing an optimized compare-and-branch
instruction An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive... |
| US-5,870,597 |
Method for speculative calculation of physical register addresses in an
out of order processor In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to... |
| US-5,870,596 |
Data processor allowing multifunctional instruction execution A data processor which allows multi-functional instruction execution has an instruction decoding unit and an instruction executing unit. The instruction decoding... |
| US-5,870,595 |
Clock-supply control system of digital-signal processors A clock-supply control system has an AND circuit whereby, when a transfer halt signal and a processing completion signal output by a DSP as well as a transfer... |
| US-5,870,594 |
Data transfer system and method The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase... |
| US-5,870,593 |
Method and programmable device for generating variable width pulse trains The present invention relates to a method for generating pulse trains by means of a microprocessor, consisting of generating an envelope signal by means of a... |
| US-5,870,592 |
Clock generation apparatus and method for CMOS microprocessors using a
differential saw oscillator A clock generation apparatus and method for generating clock signals for a microprocessor integrated circuit. The clock generation apparatus includes a device... |
| US-5,870,591 |
A/D with digital PLL A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of... |
| US-5,870,590 |
Method and apparatus for generating an extended finite state machine
architecture for a software specification A system and apparatus for generating an extended finite state machine (EFSM) from a specification expressed as a set of data relationships. The specification is... |
| US-5,870,589 |
Method for enhanced broadcast and unknown server operation Provided are a method and system for achieving enhanced performance in communications involving one or more emulated networks overlaid onto at least one base... |
| US-5,870,588 |
Design environment and a design method for hardware/software co-design A hardware and software co-design environment and design methodology based on a data-model that allows one to specify, simulate, and synthesize heterogeneous... |
| US-5,870,587 |
Information-handling system, method, and article of manufacture
including a mechanism for providing an improved... An information-handling system is disclosed that includes an improved application programmatic interface that allows application binary interfaces to be ported... |
| US-5,870,586 |
Configuration emulation of a programmable logic device A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a... |
| US-5,870,585 |
Design for a simulation module using an object-oriented programming
language A register transfer level (RTL) model is created using an object-oriented programming language. In that RTL model, a logic circuit can be represented by a... |
| US-5,870,584 |
Method and apparatus for sorting elements The present invention pertains to a method for sorting. The method comprises the steps of forming a decision tree comprised of at least a first level having at... |
| US-5,870,583 |
Method of editing information for managing recordable segments of a
recording medium where scanned and... A memory controller is equipped with a memory data search circuit for carrying out an identifying operation of management information corresponding to a segment... |
| US-5,870,582 |
Method and apparatus for completion of non-interruptible instructions
before the instruction is dispatched In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor... |
| US-5,870,581 |
Method and apparatus for performing concurrent write operations to a
single-write-input register file and an... A microchip has a register file having a plurality of registers and an accumulator register connected in parallel with the register file that allow write... |
| US-5,870,580 |
Decoupled forwarding reorder buffer configured to allocate storage in
chunks for instructions having unresolved... A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding... |
| US-5,870,579 |
Reorder buffer including a circuit for selecting a designated mask
corresponding to an instruction that results... A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. The reorder buffer stores speculatively executed... |
| US-5,870,578 |
Workload balancing in a microprocessor for reduced instruction dispatch
stalling A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the... |
| US-5,870,577 |
System and method for dispatching two instructions to the same execution
unit in a single cycle When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches... |
| US-5,870,576 |
Method and apparatus for storing and expanding variable-length program
instructions upon detection of a miss... Methods apparatus for storing and expanding wide instruction words in a computer system are provided. The computer system includes a memory and an instruction... |
| US-5,870,575 |
Indirect unconditional branches in data processing system emulation mode A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described.... |
| US-5,870,574 |
System and method for fetching multiple groups of instructions from an
instruction cache in a RISC processor... A system and method for fetching instructions for use in a RISC processor having an on-chip instruction cache is disclosed. The system accesses a first group of... |
| US-5,870,573 |
Transistor switch used to isolate bus devices and/or translate bus
voltage levels A plurality of MOSFET switches, one per bus line, are used to solve the problem of interfacing between two incompatible devices via a single shared bus. The... |
| US-5,870,572 |
Universal buffered interface for coupling multiple processors, memory
units, and I/O interfaces to a common... A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least... |
| US-5,870,571 |
Automatic control of data transfer rates over a computer bus In a computer with an UltraSCSI bus system, an arrangement is provided for reducing the possibility of the SCSI specifications being exceeded. This arrangement... |
| US-5,870,570 |
Multiple bus agent integrated circuit device for connecting to an
external bus A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple... |
| US-5,870,568 |
Double buffering operations between the memory bus and the expansion bus
of a computer system Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system... |
| US-5,870,567 |
Delayed transaction protocol for computer system bus A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access... |
| US-5,870,566 |
Port expansion network and method for lan hubs An expandable local area hub network is provided by the present invention. The network comprises a plurality of hubs interconnected for direct communication.... |
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