Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-5,870,360 |
Disc recording and/or reproducing apparatus having disc exchange function A disc recording/reproducing apparatus for selectively taking out a disc housed within a housing unit for recording or reproducing information signals on or from... |
| US-5,870,359 |
Disc holder for a disc reproducing device A disc holder has a support portion comprising arcuated portions. The arcuated portions include opposite upper portions the curvature of which is substantially... |
| US-5,870,358 |
Disk recording/reproducing apparatus having magazine for accommodating a
plurality of disks and a tray position... A disk recording/reproducing apparatus has an improved structure such that a disk seated on a disk seating unit is inserted between rollers for transferring the... |
| US-5,870,357 |
Multidisk CD-storage, retrieval, and playback system including an
elevator system having a gripper and front... A multidisk CD storage, retrieval, and playback system and process of operation is described. The system contains a storage magazine containing a multiplicity of... |
| US-5,870,356 |
Optical storage apparatus which detects a lens position signal without a
lens position sensor When a pull-in to a target track due to a turn-on of a tracking servo unit fails and a seek error is detected, a seek error processing unit turns on, for... |
| US-5,870,355 |
CD-ROM device capable of reproducing both audio data and computer data A CD-ROM device has an audio data buffer and a computer data buffer. The audio data is read into the audio data buffer at a speed higher than required for audio... |
| US-5,870,354 |
Data recording and reproducing apparatus capable of detecting an input
for controlling an output A data storing/reproducing apparatus includes a storing unit for storing inputted data, a range designating unit for designating an arbitrary range within the... |
| US-5,870,353 |
Magneto-optic recording medium, having the lands and grooves magnetized
in one direction A high-quality magneto-optic signal is obtained by setting an optimum phase condition at the time of reproducing the land or groove record in a magneto-optic... |
| US-5,870,352 |
DC monitor for active device speed Methods and circuits to measure the speed of silicon test structures using direct current test equipment. Each test structure comprises an oscillator and a... |
| US-5,870,351 |
Broadband microfabriated ultrasonic transducer and method of fabrication A broadband microfabricated ultrasonic transducer which includes a plurality of resonant membranes of different sizes and/or shapes supported above a conductive... |
| US-5,870,350 |
High performance, high bandwidth memory bus architecture utilizing SDRAMs A high performance, high bandwidth memory bus architecture and module. The module may be a card that includes standard synchronous DRAM (SDRAM) chips and reduces... |
| US-5,870,349 |
Data processing system and method for generating memory control signals
with clock skew tolerance The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which... |
| US-5,870,348 |
Dynamic semiconductor memory device having excellent charge retention
characteristics Level converter converts a word line group specifying signal, which is sent from a row decoder and has amplitude of a power supply potential Vcc and a ground... |
| US-5,870,347 |
Multi-bank memory input/output line selection A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row... |
| US-5,870,346 |
VLSI memory circuit A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge... |
| US-5,870,345 |
Temperature independent oscillator An improved oscillator circuit 400 having a frequency that is substantially independent of temperature. The improved oscillator circuit is particularly well... |
| US-5,870,344 |
Semiconductor memory device A semiconductor memory device has a memory cell array having a plurality of memory cells connected to multiple word lines and between multiple pairs of bit... |
| US-5,870,343 |
DRAM sensing scheme for eliminating bit-line coupling noise A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one... |
| US-5,870,342 |
Semiconductor memory device surely reset upon power on A mode setting signal generating circuit activates mode setting signals in accordance with external signals. A test mode activating signal generating circuit... |
| US-5,870,341 |
Memory column redundancy circuit A memory circuit which steers read/write data to a memory array including a plurality of columns (at least one of which is redundant). Coupled to the bit line of... |
| US-5,870,340 |
Multiplexer A semiconductor integrated circuit device has a data selecting circuit connected to a first power supply terminal, a precharge circuit, connected to a second... |
| US-5,870,339 |
MOS semiconductor device with memory cells each having storage capacitor
and transfer transistor A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an... |
| US-5,870,338 |
Circuit and method for reading and writing data in a memory device A memory device. The memory device includes an array of memory cells that are coupled to a number of word lines and a number of digit lines. The memory device... |
| US-5,870,337 |
Flash-erasable semiconductor memory device having an improved reliability A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for... |
| US-5,870,336 |
Memory with improved reading time To improve the reading time of a memory, it is determined when a word line will be completely charged by making an additional memory cell, connected to an... |
| US-5,870,335 |
Precision programming of nonvolatile memory cells An integrated circuit memory system and method for precision hot carrier injection programming of single or plurality of nonvolatile memory cells is described.... |
| US-5,870,334 |
Nonvolatile semiconductor memory device In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells,... |
| US-5,870,333 |
Read voltage control device for semiconductor memory device A write pulse generating unit for generating write pulses having variable wavelengths is provided. A write pulse having a variable wavelength, generated from the... |
| US-5,870,332 |
High reliability logic circuit for radiation environment A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied... |
| US-5,870,331 |
Application-specific SRAM memory cell for low voltage, high speed
operation An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at... |
| US-5,870,330 |
Method of making and structure of SRAM storage cell with N channel thin
film transistor load devices An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the... |
| US-5,870,329 |
Enhanced ASIC process cell A DRAM bit storage cell comprising a pair of capacitors each having one plate connected to a source or drain of a pass FET, another plate of a first of the pair... |
| US-5,870,328 |
Bistable magnetic element and method of manufacturing the same In a bistable magnetic element, a pulse current or a dc-biased high frequency current is supplied to a soft magnetic material which has a helical magnetic... |
| US-5,870,327 |
Mixed mode RAM/ROM cell using antifuses A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is... |
| US-5,870,326 |
Information encoding by multiple line selection An improved storage circuit that allows multiple bits to be encoded and stored using a single storage element. The encoded information is defined by a coupling... |
| US-5,870,325 |
Memory system with multiple addressing and control busses A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple... |
| US-5,870,324 |
Contents-addressable memory The invention relates to a contents-addressable memory (CAM) with multiple logical-memory arrays Di. The logical-memory arrays Di are distributed logically in... |
| US-5,870,323 |
Three overlapped stages of radix-2 square root/division with speculative
execution In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8... |
| US-5,870,322 |
Multiplier to selectively perform unsigned magnitude multiplication or
signed magnitude multiplication A multiplier for selectively performing an unsigned magnitude multiplication or a signed magnitude multiplication with a modified Booth algorithm for a... |
| US-5,870,321 |
Method and apparatus to reduce the size of rom used in mathematical
computatiions A method and apparatus for implementing mathematical functions of the nature of f(x). The range of values for the value of x (e.g., from 1 to 2 when x is... |
| US-5,870,320 |
Method for reducing a computational result to the range boundaries of a
signed 16-bit integer in case of overflow The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using... |
| US-5,870,319 |
Device and method for collecting data from graphed images A computing device (10) for capturing designated data from one or more graphic applications (60) comprising a screen area (16) for viewing one or more graphic... |
| US-5,870,318 |
Computers with a proof function The inventive computer includes a RAM which sequentially stores a series of calculation expression data thereto, a proof unit which proves the series of... |
| US-5,870,317 |
Remote and proximal interlock testing mechanisms and testing systems This invention relates to a novel process with attendant methods and apparatus for testing interlocks on machine barrier guards or equivalent safeguards. The... |
| US-5,870,316 |
Methods of using simultaneous test verification software Methods of speeding error analysis of electronic devices under test using simulation software that has the capability of simultaneously executing up to 32 tests... |
| US-5,870,315 |
Apparatus and method for determining vehicle wheel alignment
measurements from three dimensional wheel... Apparatus and method for determining the alignment positions and orientations of vehicle wheels includes optical targets mounted on the wheels and optical... |
| US-5,870,313 |
Optimization processing for integrated circuit physical design
automation system using parallel moving windows One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A... |
| US-5,870,312 |
Advanced modular cell placement system with dispersion-driven levelizing
system A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The... |
| US-5,870,311 |
Advanced modular cell placement system with fast procedure for finding a
levelizing cut point A system for defining a cut point dividing a plurality of cells located on the surface of a semiconductor chip is disclosed herein. The surface has at least one... |
| US-5,870,310 |
Method and apparatus for designing re-usable core interface shells Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one... |
Copyright 2008−2012 Patents.com
