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| Patent # | Description |
|---|---|
| US-5,923,626 |
Recording or playback devices for optical information carriers having a
different track width The present invention to provides for information carriers of different storage densities, a recording and/or playback device which is compatible or can be used... |
| US-5,923,625 |
Magneto-optical recording medium and method for recording and
reproduction thereon A magneto-optical recording medium and a method for recording and reproduction thereon are provided in order to reproduce information recorded by multi-valued... |
| US-5,923,624 |
Radio receiver including a recording unit for audio data A car radio having a removable operating part and a recording unit for audio signals, the recording unit being arranged in the operating part. A microphone... |
| US-5,923,623 |
Means for detachably attaching ornamental container to wrist watch An arrangement for detachably attaching an ornamental container to a wrist watch includes a supporting frame for the ornamental container to detachably connect... |
| US-5,923,622 |
Watch case back cover assembly A watch case back cover assembly includes a case back cover removably mounted to a case frame, an elastic member, and a cover plate. The case back cover includes... |
| US-5,923,621 |
Clock doubler circuit with duty cycle control A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a... |
| US-5,923,620 |
Module structure and electronic device A baseplate-free module includes a circuit board 1 held between housings 41 and 42. The circuit board 1 has engaging holes 17 in which hooks 41a, 42a of the... |
| US-5,923,619 |
Generator A generator, for miniature power consuming devices in particular, comprises a rotor wheel (4), which is coupled to a driven shaft and which has magnetized poles,... |
| US-5,923,618 |
Leap-second cure for 1999 GPS rollover problem The timing system for GPS has a week counter that recycles at intervals of about 20 years. The first recycling will occur on Aug. 22, 1999, producing a time... |
| US-5,923,617 |
Frequency-steered acoustic beam forming system and process A sonar system includes a pulse generator that produces an electrical signal having a plurality of frequencies. An acoustic radiator formed as a first blazed... |
| US-5,923,616 |
Communication coil housing for a solid marine seismic cable A solid marine seismic cable assembly includes communication coil housings which clamp around a cable in a spaced-apart relationship. The cable has a central... |
| US-5,923,615 |
Synchronous pipelined burst memory and method for operating same A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which... |
| US-5,923,614 |
Structure and method for reading blocks of data from selectable points
in a memory device A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option... |
| US-5,923,613 |
Latched type clock synchronizer with additional 180.degree.-phase shift
clock A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is... |
| US-5,923,612 |
Synchronous semiconductor memory device having macro command storage and
execution method therefor A semiconductor memory device having a macro command function includes a macro storage section for storing a series of external instructions synchronized with a... |
| US-5,923,611 |
Memory having a plurality of external clock signal inputs A method and apparatus for operating a synchronous memory from a plurality of external clock signals is described. By providing external system, read, and write... |
| US-5,923,610 |
Timing scheme for memory arrays A DRAM includes a data input buffer having a first input terminal coupled to data I/O pins, a second input terminal coupled to a column address buffer, a third... |
| US-5,923,609 |
Strobed wordline driver for fast memories A wordline driver for a semiconductor memory array having a circuit for selecting and deselecting the first end of an addressed wordline and a circuit for... |
| US-5,923,608 |
Scalable N-port memory structures A scalable N-port memory device using as a building block a dual-port memory device core. The dual-port memory has two ports each of which can either serve as a... |
| US-5,923,607 |
Apparatus and method for enlarging metal line pitch of semiconductor
memory device An apparatus and a method for enlarging a metal line pitch of a semiconductor memory device. The metal line enlargement apparatus comprises a first transfer... |
| US-5,923,606 |
NOR-type mask ROM having dual sense current paths A NOR-type mask ROM reduces the resistance ratio of buried diffusion layers and improves the drive capacity of bank selection transistors by utilizing sub-bit... |
| US-5,923,605 |
Space-efficient semiconductor memory having hierarchical column select
line architecture Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa,... |
| US-5,923,604 |
Method and apparatus for anticipatory selection of external or internal
addresses in a synchronous memory device A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external... |
| US-5,923,603 |
Equilibrate circuit for dynamic plate sensing memories The present invention is directed to a circuit for equilibrating a bitline and a plateline of a dynamic plate sensing memory device. The circuit includes a first... |
| US-5,923,602 |
Method for testing floating gate cells A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing... |
| US-5,923,601 |
Memory array sense amplifier test and characterization A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A... |
| US-5,923,600 |
Semiconductor device and test method and apparatus for semiconductor
device A semiconductor device having a multi-bit data input/output terminal is tested or inspected by use of a conventional testing apparatus. The semiconductor device... |
| US-5,923,599 |
Apparatus and method for subarray testing in dynamic random access
memories using a built-in-self-test unit In a built-in-self-test (BIST) unit or a memory unit, an address limits unit is provided which, prior to initiation of the test procedures, has start and stop... |
| US-5,923,598 |
Row fuse detect circuit A row identification circuit identifies which redundant-row fuse has been blown in a memory integrated-circuit by electrically interrogating the ... |
| US-5,923,597 |
Dynamically variable digital delay line A dynamically variable digital delay line includes a storage element, write control circuitry, read control circuitry and output rate control circuitry.... |
| US-5,923,596 |
Precharge-enable self boosting word line driver for an embedded DRAM A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a... |
| US-5,923,595 |
Synchronous DRAM including an output data latch circuit being controlled
by burst address A synchronous DRAM for high-speed operation does not apply a burst address to a column address buffer under SDRAM's burst mode operation which receives only an... |
| US-5,923,594 |
Method and apparatus for coupling data from a memory device using a
single ended read data path A single ended read data path in a memory device is described for providing a data signal from a cell in a memory array to a data output terminal. A single... |
| US-5,923,593 |
Multi-port DRAM cell and memory system using same A multi-port DRAM cell structure that enables read, write and refresh accesses at each port of the DRAM cell. The DRAM cell includes a storage capacitor for... |
| US-5,923,592 |
Fast, low power, write scheme for memory circuits using pulsed off
isolation device A circuit, for controlling a write operation during which data from data lines is written to a memory cell, is used with a memory cell of the type that is... |
| US-5,923,591 |
Memory circuit A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for... |
| US-5,923,590 |
Device for reading cells of a memory A device for the reading of cells for a memory includes a high-gain current comparison circuit, including a first arm for the reproduction, by current mirror, of... |
| US-5,923,589 |
Non-volatile semiconductor memory device having long-life memory cells
and data erasing method A non-volatile semiconductor memory device is provided that includes a split gate type memory cell and a control unit. The split gate type memory cell has a... |
| US-5,923,588 |
Non-volatile semiconductor memory device with a plurality of programming
voltage levels In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The... |
| US-5,923,587 |
Multi-bit memory cell array of a non-volatile semiconductor memory
device and method for driving the same A memory cell array of a non-volatile semiconductor memory device includes unit strings grouped into first strings belonging to a first string group and second... |
| US-5,923,586 |
Nonvolatile memory with lockable cells Disclosed is a nonvolatile memory having lockable cell array. The memory includes a lockable cell array formed of a plurality of lockable cell transistors and... |
| US-5,923,585 |
Source biasing in non-volatile memory having row-based sectors A non-volatile memory includes an array of memory cells that is partitioned into sectors with sources of memory cells in each sector coupled together but... |
| US-5,923,584 |
Dual poly integrated circuit interconnect An electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the... |
| US-5,923,583 |
Ferromagnetic memory based on torroidal elements A magnetic memory cell for storing binary encoded data and a memory constructed from these memory cells. The memory cell stores information in the direction of... |
| US-5,923,582 |
SRAM with ROM functionality A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a... |
| US-5,923,581 |
Information recording medium, reading apparatus for said medium and
processes for implementing said apparatus Information recording medium, reading apparatus for said medium and processes for implementing the apparatus. According to the invention, the material... |
| US-5,923,580 |
Semiconductor memory For reducing the area for read/write bus lines to a half and shortening the length of the read/write bus lines so as to speed up the operation, the locating... |
| US-5,923,579 |
Optimized binary adder and comparator having an implicit constant for an
input A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation... |
| US-5,923,578 |
Data processing circuit A data processing circuit multiplies, by 2.sup.a, input data supplied in a time-division multiplexed manner over a plurality of lines. The data processing... |
| US-5,923,577 |
Method and apparatus for generating an initial estimate for a floating
point reciprocal An initial estimate of a reciprocal of a floating point number is generated in one addition having correct sign, exponent and up to five or more bits of... |
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