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| Patent # | Description |
|---|---|
| US-5,924,027 |
Best-chance routing An improved cellular communications system and method is disclosed which routes incoming calls to those subscribers who do not answer their page. The incoming... |
| US-5,924,026 |
Exchange of system and terminal capabilities over the same analog
control channel A method for exchanging protocol support information between a base station and a mobile station over an analog control channel. The method includes a first step... |
| US-5,924,025 |
System and method for detection of redial fraud in a cellular telephone
system A system analyzes telephone calls that have been determined by signature analysis to be fraudulent and stores parameter data associated with the fraudulent cell... |
| US-5,924,024 |
Method and circuit for achieving frequency conversion A frequency conversion method and a frequency conversion circuit which enlarge the frequency difference between the upper and lower sidebands of the output... |
| US-5,924,023 |
Channel operation monitoring in cellular communications networks In order to test the performance of a mobile communications channel, the occurrences of active signals and interference signals are analyzed to determine a... |
| US-5,924,022 |
RF repeater for TDMA mobile telephone systems An RF repeater for exchanging time division multiple access (TDMA) transmit and receive signals between a mobile handset and a CATV plant or other signal conduit... |
| US-5,924,021 |
Frequency conversion circuit and method for millimeter wave radio A frequency upconversion circuit in a millimeter wave radio transmitter uses a low frequency synthesizer and a parallel frequency mixing and multiplication... |
| US-5,924,020 |
Antenna assembly and associated method for radio communication device An antenna assembly, and an associated method, which exhibits a selected the antenna beam configuration. The direction of a primary lobe and of a null is... |
| US-5,924,019 |
Radio frequency switch including voltage multiplier A radio frequency switch includes a field-effect-transistor (FET) having a gate connected to a voltage multiplier. The control voltage for the switch is... |
| US-5,924,018 |
Analog microwave communication system having a microwave hop converted
to a new operating frequency and method A converted analog radio (71) is disclosed for converting an analog microwave hop (70) to a new operating frequency. The converted analog radio (71) comprises an... |
| US-5,924,017 |
Method and system for adaptively setting wake-up intervals in paging
devices In a paging system, a central paging station determines a preferred amount of time, or "sleep value," that a paging device is to be inactive during a paging... |
| US-5,924,016 |
Control and monitoring apparatus and method for a telephone system A telephone switching and control system connected to a telephone network for providing telephone calling services to an authorized user. The telephone switching... |
| US-5,924,015 |
Power control method and apparatus for satellite based
telecommunications system A power control method and apparatus are provided for a satellite based telecommunications system. The system includes a power control subsystem which is... |
| US-5,924,014 |
Method and apparatus for adaptive routing in a satellite-based
communication system In satellite based communication systems (30), real time monitoring of communication links (23-25) and the subsequent adaptations to overcome problems with... |
| US-5,924,013 |
Method and apparatus for transmitting motion picture cinematic
information for viewing in movie theaters and... Cinematic information including cinemagraphic video images and, optionally, corresponding audio data are converted into a digital format and RF transmitted from... |
| US-5,924,012 |
Methods, complexes, and system for forming metal-containing films A method of forming a film on a substrate using Group III metal complexes. The complexes and methods are particularly suitable for the preparation of ... |
| US-5,924,011 |
Silicide process for mixed mode product A method is disclosed for fabricating mixed analog/digital devices without incurring detrimental effects of high temperature forming of analog components such as... |
| US-5,924,010 |
Method for simultaneously fabricating salicide and self-aligned barrier A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and... |
| US-5,924,009 |
Titanium silicide interconnect method A technology of forming a semiconductor integrated device is disclosed. According to the technology, titanium silicide is formed from an interaction between a... |
| US-5,924,008 |
Integrated circuit having local interconnect for reducing signal cross
coupled noise An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is... |
| US-5,924,007 |
Method for improving the planarization of inter-poly dielectric A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere... |
| US-5,924,006 |
Trench surrounded metal pattern A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device... |
| US-5,924,005 |
Process for forming a semiconductor device A low dielectric constant (k) polymer is used for an interlayer dielectric (28) of a semiconductor device (20). Unlike prior art low k polymer materials, a... |
| US-5,924,004 |
Manufacturing method for forming metal plugs A method for forming metal plugs using fewer masks and photolithographic processes than a conventional one and therefore able to simplify the overall... |
| US-5,924,003 |
Method of manufacturing ball grid arrays for improved testability A ball grid array package for integrated circuit chips that is designed to facilitate testing. The balls are planarized with high precision to make electrical... |
| US-5,924,002 |
Method of manufacturing a semiconductor device having ohmic electrode A semiconductor device having an ohmic electrode having a satisfactory ohmic contact to an n-type GaAs can be obtained by heat treatment at low temperature. A... |
| US-5,924,001 |
Ion implantation for preventing polycide void A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of... |
| US-5,924,000 |
Method for forming residue free patterned polysilicon layer containing
integrated circuit structures A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having... |
| US-5,923,999 |
Method of controlling dopant diffusion and metal contamination in thin
polycide gate conductor of mosfet device A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a... |
| US-5,923,998 |
Enlarged align tolerance in buried contact process using sidewall spacer A method of manufacturing a buried contact is disclosed, wherein a thin silicon oxide layer is formed on the silicon substrate. The thin oxide functions as a... |
| US-5,923,997 |
Semiconductor device One kind or plural kinds of elements selected from a groups III, IV or V elements are introduced in an amorphous silicon film, and then crystallized by heating... |
| US-5,923,996 |
Method to protect alignment mark in CMP process A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical... |
| US-5,923,995 |
Methods and apparatuses for singulation of microelectromechanical systems Disclosed are methods and apparatuses that allow the dicing of wafers containing microelectromechanical systems into singulated individual dies that is economic... |
| US-5,923,994 |
Selective oxidation process A selective oxidation process includes conducting a former phase of an oxidation process employing a thick mask layer to produce an oxide layer having a... |
| US-5,923,993 |
Method for fabricating dishing free shallow isolation trenches A fabrication process for manufacturing integrated circuits with isolation trenches. The process includes the use of two nitride layers and an oxide layer formed... |
| US-5,923,992 |
Integrated circuit formed with shallow isolation structures having
nitride placed on the trench dielectric A method for protecting the trench dielectric fill for a shallow trench isolation structure by forming a protective layer upon the upper surface of the trench... |
| US-5,923,991 |
Methods to prevent divot formation in shallow trench isolation areas A number of methods to prevent divot formation, and the resulting enhanced electric field associated therewith, are disclosed. In a first embodiment of the... |
| US-5,923,990 |
Process for positioning a mask relative to a workpiece To increase operating efficiency and prevent operating errors, such as adjustment errors and the like, by automatic computation of the distance between the... |
| US-5,923,989 |
Method of fabricating rugged capacitor of high density DRAMs A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and... |
| US-5,923,988 |
Two step thermal treatment procedure applied to polycide structures
deposited using dichlorosilane as a reactant A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of... |
| US-5,923,987 |
Method for forming MOS devices with retrograde pocket regions and
counter dopant regions at the substrate surface Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high... |
| US-5,923,986 |
Method of forming a wide upper top spacer to prevent salicide bridge A method of forming a wide top spacer (50 20S 40A) that prevents salicide bridging. The wide top spacer (50) consists of a first spacer (20S) and an upper spacer... |
| US-5,923,985 |
MOS field effect transistor and its manufacturing method A method of manufacturing a MOS field effect transistor comprises forming on a semiconductor substrate a first epitaxial growth layer having an impurity doping... |
| US-5,923,984 |
Method of making enhancement-mode and depletion-mode IGFETS with
different gate materials A method of making enhancement-mode and depletion-mode IGFETs with different gate materials is disclosed. The method includes providing a semiconductor substrate... |
| US-5,923,983 |
Integrated circuit gate conductor having a gate dielectric which is
substantially resistant to hot carrier effects An integrated circuit is formed whereby transistor gate dielectrics are made less susceptible to hot carrier effects. Barrier atoms are inserted into critical... |
| US-5,923,982 |
Method of making asymmetrical transistor with lightly and heavily doped
drain regions and ultra-heavily doped... A method of making the IGFET includes providing a semiconductor substrate, providing a gate over the semiconductor substrate, implanting lightly doped source and... |
| US-5,923,981 |
Cascading transistor gate and method for fabricating the same A cascading transistor gate structure and method for fabricating the same are disclosed. A substrate is provided, and a layer of gate dielectric material is... |
| US-5,923,980 |
Trench transistor with localized source/drain regions implanted through
voids in trench A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom... |
| US-5,923,979 |
Planar DMOS transistor fabricated by a three mask process A planar DMOS power transistor (MOSFET) fabricated using only three masking steps, resulting in a significant reduction in fabrication cost. The resulting device... |
| US-5,923,978 |
Nonvolatile semiconductor memory and methods for manufacturing and using
the same A nonvolatile semiconductor memory is composed of a number of multi-bit memory cells, each including a first floating gate and a second floating gate formed,... |
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