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| Patent # | Description |
|---|---|
| US-6,085,300 |
DRAM system with simultaneous burst read and write A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no... |
| US-6,085,299 |
Secure updating of non-volatile memory A secure start-up system for a computer enables a flash memory to be reset in a secured way. Various operations are carried out to make sure that the reset is an... |
| US-6,085,298 |
Comparing mass storage devices through digests that are representative
of stored data in order to minimize data... A system and method for comparing mass storage devices. Generally, a mass storage device is subdivided into data blocks representing physical storage locations... |
| US-6,085,297 |
Single-chip memory system including buffer To operate faster, a memory system includes a central processing unit (CPU) for executing a first instruction, and for outputting first, second and third... |
| US-6,085,296 |
Sharing memory pages and page tables among computer processes A method of managing computer memory pages. The sharing of a program-accessible page between two processes is managed by a predefined mechanism of a memory... |
| US-6,085,295 |
Method of maintaining data coherency in a computer system having a
plurality of interconnected nodes A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list... |
| US-6,085,294 |
Distributed data dependency stall mechanism A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is... |
| US-6,085,293 |
Non-uniform memory access (NUMA) data processing system that decreases
latency by expediting rerun requests A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a... |
| US-6,085,292 |
Apparatus and method for providing non-blocking pipelined cache A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that... |
| US-6,085,291 |
System and method for selectively controlling fetching and prefetching
of data to a processor Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a... |
| US-6,085,290 |
Method of and apparatus for validating data read out of a multi port
internally cached dynamic random access... An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation... |
| US-6,085,289 |
Method and system for load data formatting and improved method for cache
line organization An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter... |
| US-6,085,288 |
Dual cache directories with respective queue independently executing its
content and allowing staggered write... A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with... |
| US-6,085,287 |
Method and apparatus for enhancing the disk cache process by dynamically
sizing prefetch data associated with... The performance of a disk cache subsystem is enhanced by dynamically sizing read requests based upon the current disk cache hit rate. Any data requested in the... |
| US-6,085,286 |
Cache control method and apparatus In an information processing system having a data processing apparatus, a control unit for a cache memory, and a storage unit for storing a record, respectively... |
| US-6,085,285 |
Intermixing different devices along a single data communication link by
placing a strobe signal in a parity bit... A data storage system is described which allows data storage devices with different characteristics, such as differing data rates and transfer speeds, to be... |
| US-6,085,284 |
Method of operating a memory device having a variable data output length
and an identification register A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification... |
| US-6,085,283 |
Data selecting memory device and selected data transfer device A selective data memory device includes skip and sequential read circuits that connect input/output lines for inputting and outputting string data, and data set... |
| US-6,085,282 |
Method and apparatus for distinguishing register reads from memory reads
in a flash memory A non-volatile memory (12) such as FLASH provides for two modes of operation: command mode and memory mode. Read requests in command mode read non-volatile... |
| US-6,085,281 |
Method and a device for performing a flash EEPROM An initiating processing unit is normally occupied during the programming of flash EEPROMs. The time of occupation becomes ever longer with increasing age and... |
| US-6,085,280 |
Parallel-access memory and method A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to... |
| US-6,085,279 |
Interrupt control system provided in a computer An interrupt control system is provided in a computer having a processor, a PCI bus, an ISA bus, and a serial transfer line. An interrupt controller outputs... |
| US-6,085,278 |
Communications interface adapter for a computer system including posting
of system interrupt status To facilitate access of interrupt status information, interrupt posting status. POST.sub.-- STAT registers are readable by a host driver routine to quickly... |
| US-6,085,277 |
Interrupt and message batching apparatus and method An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O... |
| US-6,085,276 |
Multi-processor computer system having a data switch with simultaneous
insertion buffers for eliminating... An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of... |
| US-6,085,275 |
Data processing system and method thereof A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations... |
| US-6,085,274 |
Computer system with bridges having posted memory write buffers A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management... |
| US-6,085,273 |
Multi-processor computer system having memory space accessible to
multiple processors A multi-processor computer system comprises one or more CPUs (1) connected to a host computer (2) via a common PCI bus system backplane (3). The host computer... |
| US-6,085,272 |
Transmitting command block data using the lower address part of the
address phase Apparatus and methods are defined for increasing the effective bandwidth of a system bus for commanding a co-processor in an information processing system. The... |
| US-6,085,271 |
System bus arbitrator for facilitating multiple transactions in a
computer system A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction... |
| US-6,085,270 |
Multi-channel, multi-rate isochronous data bus An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into... |
| US-6,085,269 |
Configurable expansion bus controller in a microprocessor-based system A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128)... |
| US-6,085,268 |
Portable information terminal/method for renewing programs using PC card
with utility programs on PC card... A portable information terminal capable of updating a program using a PC card, and a method for updating a program using the same, are provided. The portable... |
| US-6,085,267 |
Method of and apparatus for recording information on record medium, and
apparatus for reproducing the same A recording apparatus for recording information on a record medium is provided with: a controller for generating a start address of each time-unit piece of main... |
| US-6,085,266 |
System for unwrapping a single file from a compact disk for utilization
by various computer platforms A system and method is provided by which byte stream data files in industry-standard format can be retrieved from a compact disk and then re-created to provide... |
| US-6,085,265 |
System for handling an asynchronous interrupt a universal serial bus
device A system and method for establishing communication between a host computer and a peripheral device. The host computer includes logic for associating an attached... |
| US-6,085,264 |
Accounting-information outputting device An accounting-process-type setting program is executed and thereby an accounting-record outputting condition is set. Then, when execution of an execution unit is... |
| US-6,085,263 |
Method and apparatus for employing commit-signals and prefetching to
maintain inter-reference ordering in a... An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O... |
| US-6,085,262 |
Hierarchical data storage processing apparatus for partitioning resource
across the storage hierarchy The present invention relates to a data storage processing apparatus and the object of the present invention is to provide storages including off-line media and... |
| US-6,085,261 |
Method and apparatus for burst protocol in a data processing system A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion... |
| US-6,085,260 |
Method and circuit for multiplexing an input port and an output port of
a microprocessor into a single external... A method and circuit interface for multiplexing an input port and an output port of a microprocessor into a single external interface, wherein the input port and... |
| US-6,085,259 |
Addressing apparatus and method An addressing apparatus and a corresponding method are described, such that addressing of network components, which are connected via a bus and which each have... |
| US-6,085,258 |
State machine for selectively performing an operation on a single or a
plurality of registers depending upon... A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled... |
| US-6,085,257 |
Enhanced receiving chip for a computer monitor An improved transceiver that is tightly integrated into an enhanced receiving chip for a computer monitor. The transceiver includes a receiver having a first... |
| US-6,085,256 |
Cyber space system for providing a virtual reality space formed of three
dimensional pictures from a server to... A cyber-space system comprising one or more cyber-spaces for providing predetermined information, and user terminals for receiving provision of the predetermined... |
| US-6,085,255 |
System and associated method for re-engineering a telecommunications
support system with object-oriented... A re-engineering method for standardizing data processing in a communication network while maintaining user services is disclosed. Data channels, between... |
| US-6,085,254 |
Dynamic size alteration of memory files A method and system for use primarily, but not exclusively, in digital communications switching systems are disclosed, in which the size of traffic-sensitive... |
| US-6,085,253 |
System and method for transmitting and receiving data The present invention provides a system and method for transmitting and receiving data that can transmit data over a plurality of data paths simultaneously and... |
| US-6,085,252 |
Device, system and method for real-time multimedia streaming The present invention provides a device (200, 300), system (400, 500) and method for real-time streaming of a multimedia file stored in a remote server over a... |
| US-6,085,251 |
Implementing a parallel file transfer protocol Apparatus and method to improve the speed of electronic file transfer between remote computers by parallel processing. The most common transfer protocol is the... |
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