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| Patent # | Description |
|---|---|
| US-6,085,351 |
Synchronization method The method of synchronizing a receiver in a coded data transmission by means of an M-stage channel symbol alphabet, which includes dividing the channel symbol... |
| US-6,085,350 |
Single event upset tolerant system and method An single event upset (SEU) tolerant system for detecting and correcting an SEU includes a decision element (200) for receiving a plurality of outputs (120) from... |
| US-6,085,349 |
Method for selecting cyclic redundancy check polynomials for linear
coded systems The method for selecting CRC polynomials (or CRC generators) for linear coded systems. In the exemplary embodiment, a communication system utilizes a... |
| US-6,085,348 |
Error correction code encoder and decoder Error correction code (ECC) encoding is performed by using a first ECC encoding means to add a first check code to each of a number of first code groups included... |
| US-6,085,347 |
System and method for enhancing modem performance using digital signal
processing techniques DSP error detection and filtering of a modem signal using a simple, robust, and low cost technique. The DSP technique utilizes a equalizer/filter to adjust the... |
| US-6,085,346 |
Method and apparatus for built-in self test of integrated circuits A BIST function is provided in which both the routing area devoted to the test signals and the area devoted to the circuits required to implement the BIST... |
| US-6,085,345 |
Timing control for input/output testability Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to... |
| US-6,085,344 |
Data communication interface with memory access controller A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is... |
| US-6,085,343 |
Method for concurrent testing of on-chip circuitry and timing counters A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out... |
| US-6,085,342 |
Electronic system having a chip integrated power-on reset circuit with
glitch sensor A power-on reset circuit with glitch sensing capabilities is formed as part of the same integrated circuit chip containing other logical circuits. A port... |
| US-6,085,341 |
Memory test mode for wordline resistive defects A method and apparatus for detecting resistive defects in a memory device. A pulldown device is placed at the end of a wordline opposite the end of the wordline... |
| US-6,085,340 |
Method of lattice quantization that minimizes storage requirements and
computational complexity A method of lattice-quantizing an eight-long data point to minimize storage requirements and computational complexity by acquiring the data point, multiplying... |
| US-6,085,339 |
System for memory error handling A computer system stores data according to a plurality of different error handling schemes. The computer system includes a memory controller with a plurality of... |
| US-6,085,338 |
CPI infinite and finite analysis A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction... |
| US-6,085,337 |
Method and system for reliably indicating test results during a
self-check operation A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize... |
| US-6,085,336 |
Data processing devices, systems and methods with mode driven stops A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry... |
| US-6,085,335 |
Self engineering system for use with a communication system and method
of operation therefore A self engineering system includes a data acquisition module, a self engineering engine, and a control module. The data acquisition module couples to the... |
| US-6,085,334 |
Method and apparatus for testing an integrated memory device A method of memory array testing that detects defects which are sensitive to environmental conditions. A repair signature is generated reflecting the repair... |
| US-6,085,333 |
Method and apparatus for synchronization of code in redundant
controllers in a swappable environment Methods and associated apparatus for automatically synchronizing the operating code between a plurality of controllers. In a first embodiment after the spare... |
| US-6,085,332 |
Reset design for redundant raid controllers A reset circuit implemented in a RAID controller configured for dual active operation. The reset circuit generates a reset pulse with a relatively invariant... |
| US-6,085,331 |
Setup of the time/date within the CMOS real-time-clock An apparatus for setting up a time/date of a CMOS real-time-clock within a computer system is disclosed. The computer system includes a processor, a memory, an... |
| US-6,085,330 |
Control circuit for switching a processor between multiple low power
states to allow cache snoops Power consumption is conserved in a computer system by, instead of forcing a processor to change from the stop clock state to a fully operational state, allowing... |
| US-6,085,329 |
Portable computer with low power CD-player mode A method for controlling a peripheral device in a computer system by a user that requires the CPU of the computer to be powered-on for only the short period of... |
| US-6,085,328 |
Wake up of a sleeping computer using I/O snooping and imperfect packet
filtering A reliable and simple means to awaken sleeping computers is to maintain the network interface subsystem at full power, and to filter detected packets so that... |
| US-6,085,327 |
Area-efficient integrated self-timing power start-up reset circuit with
delay of the start-up reset until the... A circuit and a method are disclosed for a power start-up reset circuit which is self-timing and which can be fully integrated in a standard CMOS or BiCMOS... |
| US-6,085,326 |
Apparatus and method for displaying DPMS mode status using an OSD circuit A method of displaying a display power management signaling (DPMS) using an on screen display (OSD) in a display device includes the steps of: determining... |
| US-6,085,325 |
Method and apparatus for supporting power conservation operation modes An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that... |
| US-6,085,324 |
Monitoring and regulatory system for the internet A regulatory system for a distributed system of computers in which authorized data files are marked with an indicia. The granting of the indicia is made by a... |
| US-6,085,323 |
Information processing system having function of securely protecting
confidential information An information processing system includes a first information processing apparatus and a second information processing apparatus arranged separate from the first... |
| US-6,085,322 |
Method and apparatus for establishing the authenticity of an electronic
document The present invention consists of a method and apparatus for authenticating an electronic document. In one embodiment of the invention, a party wishing to... |
| US-6,085,321 |
Unique digital signature A method and apparatus for a unique digital signature is provided. According to one aspect of the invention, a unique digital signature comprises an adapted... |
| US-6,085,320 |
Client/server protocol for proving authenticity A protocol for establishing the authenticity of a client to a server in an electronic transaction by encrypting a certificate with a key known only to the client... |
| US-6,085,319 |
Microcomputer reset apparatus and method A microcomputer reset apparatus including a counter for counting pulses of a pulse signal generated by a ring oscillator, and an edge detector driven by a clock... |
| US-6,085,318 |
Computer system capable of booting from CD-ROM and tape A computer system capable of booting currently manufacturable CD-ROMs or tapes without altering the ISO standard or requiring special, customized software to... |
| US-6,085,317 |
Reconfigurable computer architecture using programmable logic devices A method and system for computing using reconfigurable computer architecture utilizing logic devices is disclosed. The computing may be accomplished by... |
| US-6,085,316 |
Layered counterflow pipeline processor with anticipatory control A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different... |
| US-6,085,315 |
Data processing device with loop pipeline The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data... |
| US-6,085,314 |
Central processing unit including APX and DSP cores and including
selectable APX and DSP execution modes A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU... |
| US-6,085,313 |
Computer processor system for executing RXE format floating point
instructions A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of... |
| US-6,085,312 |
Method and apparatus for handling imprecise exceptions A method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one... |
| US-6,085,311 |
Instruction alignment unit employing dual instruction queues for high
frequency instruction dispatch A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The... |
| US-6,085,310 |
Method and apparatus for performing an operation multiple times in
response to a single instruction A method for operating a Reduced Instruction Set Computer (RISC) processor that executes mormal RISC instructions and special RISC instructions. The method... |
| US-6,085,309 |
Signal processing apparatus A signal processing apparatus executes a plurality of microprograms stored in a microprogram memory device in a time-sharing manner, so as to perform arithmetic... |
| US-6,085,308 |
Protocol processor for the execution of a collection of instructions in
a reduced number of operations Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is... |
| US-6,085,307 |
Multiple native instruction set master/slave processor arrangement and
method thereof A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control... |
| US-6,085,306 |
Processor for executing highly efficient VLIW A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field... |
| US-6,085,305 |
Apparatus for precise architectural update in an out-of-order processor A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor... |
| US-6,085,304 |
Interface for processing element array A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data... |
| US-6,085,303 |
Seralized race-free virtual barrier network Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka... |
| US-6,085,302 |
Microprocessor having address generation units for efficient generation
of memory operation addresses A microprocessor including address generation units configured to perform address generation for memory operations is provided. A reservation station associated... |
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