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| Patent # | Description |
|---|---|
| US-6,104,660 |
Battery module and battery managing system A battery module comprises at least one battery, and one or more memory sections for memorizing management information of the at least one battery at cutting... |
| US-6,104,659 |
Memory device A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator,... |
| US-6,104,658 |
Distributed DRAM refreshing Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a... |
| US-6,104,657 |
Semiconductor integrated circuit device for changing DRAM row addresses
according to operation mode A semiconductor integrated circuit device has memory cell arrays capable of using shared sense amplifiers, wherein memory can be increased by refresh units to a... |
| US-6,104,656 |
Sense amplifier control circuit in semiconductor memory A sense amplifier control circuit in a semiconductor memory supplies a sense amplifier with two power source voltages with voltage levels different from each... |
| US-6,104,655 |
Semiconductor storage device A semiconductor device that enables a reduction in power consumption and a stable operation, and which can be manufactured easily and with a high level of... |
| US-6,104,654 |
High speed sensing of dual port static RAM cell The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred... |
| US-6,104,653 |
Equilibration circuit and method using a pulsed equilibrate signal and a
level equilibrate signal An exemplary 18 MBit memory array includes four banks of array blocks. At the end of an active cycle, the exemplary memory array is automatically taken back into... |
| US-6,104,652 |
Method and memory device for dynamic cell plate sensing with AC
equilibrate A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A... |
| US-6,104,651 |
Testing parameters of an electronic device A method for testing an electronic device includes causing the device to perform an operation. Using circuitry of the device, a duration of time is ... |
| US-6,104,650 |
Sacrifice read test mode Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external... |
| US-6,104,649 |
Semiconductor memory device It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a... |
| US-6,104,648 |
Semiconductor memory device having a large band width and allowing
efficient execution of redundant repair A memory cell array includes a normal memory cell array divided into a plurality of memory blocks, a row redundant circuit and a column redundant circuit.... |
| US-6,104,647 |
Semiconductor device having redundancy circuit A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access... |
| US-6,104,646 |
Semiconductor memory device having redundancy circuit with high rescue
efficiency There is disclosed a memory cell array including regular and redundant memory cells, a plurality of bit lines connected to the regular memory cells, a plurality... |
| US-6,104,645 |
High speed global row redundancy system A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The... |
| US-6,104,644 |
Circuit for the detection of changes of address A memory is provided with an addressing circuit comprising an address bus to convey address signals, biasing and selector switch circuits connected to the... |
| US-6,104,643 |
Integrated circuit clock input buffer An integrated circuit clock buffer is described which includes output circuits for generating internal clock signals in response to an externally provided clock... |
| US-6,104,642 |
Method and apparatus for 1 of 4 register file design The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable... |
| US-6,104,641 |
Switchable multi bit semiconductor memory device In a switchable multi bit DRAM, in addition to main bit line pair and a main sense amplifier, sub bit line pair and a sub sense amplifier are provided. Between... |
| US-6,104,640 |
Electrically alterable non-violatile memory with N-bits per cell An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell is conducted by... |
| US-6,104,639 |
Memory cell with stored charge on its gate and process for the
manufacture thereof A memory cell with a stored charge on its gate, comprising (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of... |
| US-6,104,638 |
Use of erasable non-volatile memory for storage of changing information Non-volatile write-once memory, is used for storage of variable data. In an example embodiment, segmented flash memory is used, in which individual segments can... |
| US-6,104,637 |
Apparatus for programming threshold voltage for non-volatile memory cell
and method therefor An apparatus for programming a threshold-voltage of a non-volatile memory cell includes a reference voltage generator means applying a predetermined voltage to a... |
| US-6,104,636 |
Semiconductor memory which can store two or more bits of data in each
memory cell In a semiconductor memory in which each memory cell is composed of a transistor having a floating gate between a control gate and a conducting channel formed... |
| US-6,104,635 |
Non-volatile memory device readable write data latch, and internal
control thereof A non-volatile semiconductor memory device has a data latch that stores data to be written into memory cells, and functions as a sense amplifier for data read... |
| US-6,104,634 |
Electrical programmable non-volatile memory integrated circuit with
option configuration register An electrically programmable non-volatile memory integrated circuit includes: read/write resources; a first bit line; a second bit line; an option configuration... |
| US-6,104,633 |
Intentional asymmetry imposed during fabrication and/or access of
magnetic tunnel junction devices Magnetic memory cells include a changeable magnetic region with a magnetic axis along which two directions of magnetization can be imposed, thereby providing two... |
| US-6,104,632 |
Magnetic thin film memory and recording and reproducing method and
apparatus using such a memory A magnetic thin film memory includes a stack of magnetic thin film devices each comprising a first magnetic layer, a second magnetic layer of higher coercive... |
| US-6,104,631 |
Static memory cell with load circuit using a tunnel diode A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples... |
| US-6,104,630 |
Semiconductor storage device having spare and dummy word lines A memory cell array includes a plurality of memory cells that are arranged in the row and column directions. Power supply lines and grounding lines are arranged... |
| US-6,104,629 |
High frequency memory module Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal... |
| US-6,104,628 |
Integrated-circuit device with microprocessor of prescribed shape An integrated-circuit device comprises a combination of a microprocessor in the form of a circuit cell having a prescribed shape as an existing microprocessor... |
| US-6,104,627 |
Semiconductor memory device The present invention relates to a semiconductor memory device having a memory cell array of a split-operation mode. The semiconductor memory device comprises a... |
| US-6,104,626 |
Analog value memory circuit An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for... |
| US-6,104,625 |
Voltage generator A rectifier circuit 30 of a voltage genetator rectifies alternating current signals provided through electromagnetic induction of a coil. The rectified signals... |
| US-6,104,624 |
System connecting device Buck-boost type or buck type chopper circuits and transistors are employed as inverters (IV1, IV2) and power synchronizing switches (SW1, SW2), respectively. A... |
| US-6,104,623 |
Multiple output converter having secondary regulator using self-driven
synchronous rectifiers A DC--DC converter includes a transformer having at least a primary winding, a secondary winding and a drive winding. An input circuit is coupled to the... |
| US-6,104,622 |
Power supply apparatus for reduction of power consumption A power supply apparatus having an AC power supply, a transformer, a switching element and a control circuit for controlling an operation of the switching... |
| US-6,104,621 |
Torsional hinging mechanism A wireless communications device, such as a cellular telephone, is provided with a torsional hinging mechanism for rotatably coupling a flip cover to the... |
| US-6,104,620 |
Shielded radio card assembly This invention is directed to a PCMCIA Type II memory card holder assembly for a spread spectrum radio communication card that provides radio frequency... |
| US-6,104,619 |
Tape carrier package and its fabrication method therefor A tape carrier package (TCP) and method of fabricating a tape carrier package (TCP) are provided to reduce a width dimension in a slim tape carrier package (TCP)... |
| US-6,104,618 |
Structure for connecting a plurality of mutually remote electrical
components to a central unit A structure connects a plurality of mutually remote electrical components to a central unit. The components have terminal contacts that are connected through... |
| US-6,104,617 |
Extended PC card with extension connection A PC card has a sheet metal forward housing part (13) whose rear edge (36) is connected to a plastic molded rear extension part (14) before a sheet metal lower... |
| US-6,104,616 |
Modular I/O assembly system A unique cabinet mounted I/O assembly adapted for integration into a control system which allows a block I/O assembly to be mounted in both sides of the cabinet... |
| US-6,104,615 |
Semiconductor component assembly A VSMP semiconductor component is mounted by inserting an auxiliary element into a slot in a receptacle. The auxiliary element projects laterally from a narrow... |
| US-6,104,614 |
Fastening device for tight attachment between two plates A fastening device (10) includes a locking pin (12) and an associated pressing clip (14). The locking pin (12) includes a flat head (16) with ring-like shallow... |
| US-6,104,613 |
VME eurocard double printed wiring card host circuit card circuit
(module) assembly A dual-board host or main printed wiring structure of a circuit module with increased component mounting area is made plug-compatible with a VME or VME64X... |
| US-6,104,612 |
Clip-on heat sink The heat sink (10) of the present invention is used to absorb and dissipate heat from a solid-state device. The heat sink (10) comprises a generally U-shaped... |
| US-6,104,611 |
Packaging system for thermally controlling the temperature of electronic
equipment A passive method and packaging system for thermally controlling the temperature of electronic equipment within a housing are disclosed. The packaging system... |
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