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| Patent # | Description |
|---|---|
| US-6,105,161 |
Error data correction circuit An error data correction circuit is provided that increases data output speed. The error data correction circuit latches the output from an error data correction... |
| US-6,105,160 |
Packet error detecting device in a DMA transfer A packet error detecting device for detecting the existence of an error of the packet data transferred by a packet switching in a DMA transfer, comprising an... |
| US-6,105,159 |
Trellis code with improved error propagation A digital communication apparatus (20) transmits sectors of digital values that include error correction values used to detect and correct errors within the... |
| US-6,105,158 |
Screening for undetected errors in data transmission systems For a transmission system in which (a) a received sequence of symbols is processed by an inner decoder followed by an outer decoder and (b) the inner decoder is... |
| US-6,105,157 |
Salphasic timing calibration system for an integrated circuit tester An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay... |
| US-6,105,156 |
LSI tester for use in LSI fault analysis An LSI tester having a path analysis means for tracing a series of connections reversely along a designated signal flow path from one of flip-flops of DUT... |
| US-6,105,155 |
Method and apparatus for performing on-chip function checks and locating
detected anomalies within a nested... A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested... |
| US-6,105,154 |
Multi-bus multi-data transfer protocols controlled by a bus arbiter
coupled to a CRC signature compactor A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a... |
| US-6,105,153 |
Semiconductor integrated circuit and its evaluating method A semiconductor integrated circuit has a function circuit, which is composed of flip-flop (F/F) groups 1 and 1 formed by a plurality of flip-flops, a... |
| US-6,105,152 |
Devices and methods for testing cell margin of memory devices Methods for testing semiconductor memory devices are performed during the writing and reading of test information to and from memory cells. During the tests,... |
| US-6,105,151 |
System for detecting network errors A system is described for providing fault tolerance within a computer system. The system provides a method for allowing multiple network interface cards to... |
| US-6,105,150 |
Error information collecting method and apparatus A CPU in a computer includes a control information management table for storing information about whether an error has occurred in a control unit in the computer... |
| US-6,105,149 |
System and method for diagnosing and validating a machine using waveform
data The present invention discloses a system and method for diagnosing and validating a machine with waveform data generated therefrom. In this invention, historical... |
| US-6,105,148 |
Persistent state checkpoint and restoration systems By checkpointing and restoring a user application process, that includes a volatile state and a persistent state, recovery of an application process from the... |
| US-6,105,147 |
Using process pairs as transaction-coordinated resource managers The present invention is a process-pair resource manager for use in a transaction processing system. The process-pair resource manager includes a concurrent... |
| US-6,105,146 |
PCI hot spare capability for failed components A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system... |
| US-6,105,145 |
System and method for generating high resolution clockticks in a
computer system A system and method is provided by the present invention for transmitting or receiving data to or from a computer system by reprogramming the computer system's... |
| US-6,105,144 |
System and method for alleviating skew in a bus In order to transmit several data words in succession over a bus between components in a data processing system, the skew between the various bus lines has to be... |
| US-6,105,143 |
Power control device and method of controlling power of peripheral
devices of a computer system using a... A power control device of a computer system uses a universal serial bus (USB) hub for power control of a display monitor. The power control device includes: a... |
| US-6,105,142 |
Intelligent power management interface for computer system hardware A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration... |
| US-6,105,141 |
Method and apparatus for power management of an external cache of a
computer system Power management techniques for external cache memories of computers are disclosed. The power management techniques operate to reduce power consumption of an... |
| US-6,105,140 |
Secure power supply An apparatus is disclosed for protecting a computer system from an unintended or a malicious removal of power by a user. The apparatus has a power supply for... |
| US-6,105,139 |
Controller-based power management for low-power sequential circuits A low-overhead controller-based power management technique that re-specifies control signals to reconfigure existing multiplexer networks and functional units to... |
| US-6,105,138 |
Method and apparatus for controlling electric source in information
processing system A technique allowing a terminal device located in a remote place to protect data existing on an information processing system and then control an electric source... |
| US-6,105,137 |
Method and apparatus for integrity verification, authentication, and
secure linkage of software modules A method and apparatus of authenticating and verifying the integrity of software modules is disclosed. In one embodiment, said software modules initially... |
| US-6,105,136 |
Computer system which is disabled when it is disconnected from a network Described is a computer system which is coupled to a remote computer via a data communication link. The computer system has a normally closed enclosure and is... |
| US-6,105,134 |
Verification of the source of program information in a conditional
access system A cable television system provides conditional access to services. The cable television system includes a headend from which service "instances", or programs,... |
| US-6,105,133 |
Bilateral authentication and encryption system A bilateral system for authenticating remote transceiving stations through use of station identifiers (IDs), and through use of passwords which are used only one... |
| US-6,105,132 |
Computer network graded authentication system and method Methods and systems are provided which control access by a task to an information object in a computer system. The task is authenticated by an authentication... |
| US-6,105,131 |
Secure server and method of operation for a distributed information
system A secure server in a secure distributed information system isolates interaction from terminals to specific personal vaults including and to only those personal... |
| US-6,105,130 |
Method for selectively booting from a desired peripheral device Disclosed is a method for booting a computer system. The computer system includes a first device and a second device which, during initialization of the computer... |
| US-6,105,129 |
Converting register data from a first format type to a second format
type if a second type instruction consumes... A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are... |
| US-6,105,128 |
Method and apparatus for dispatching instructions to execution units in
waves A first embodiment provides an apparatus including a first execution unit capable of executing a first type and a second type of ready instruction, a second... |
| US-6,105,127 |
Multithreaded processor for processing multiple instruction streams
independently of each other by flexibly... A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for... |
| US-6,105,126 |
Address bit decoding for same adder circuitry for RXE instruction format
with same XBD location as RX format... A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first... |
| US-6,105,125 |
High speed, scalable microcode based instruction decoder for processors
using split microROM access, dynamic... A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from... |
| US-6,105,124 |
Method and apparatus for merging binary translated basic blocks of
instructions A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions... |
| US-6,105,123 |
High speed register file organization for a pipelined computer
architecture A register file organization for a pipelined microprocessor is shown which includes a pipestage register interposed a global bit line and a register cell array... |
| US-6,105,122 |
I/O protocol for highly configurable multi-node processing system A method for transferring data from a first node to a second node in a multi-processor system is described. The multi-processor system comprises a plurality of... |
| US-6,105,121 |
Data processing and data transmission system A data processing and data transmission system, in which a personal computer is coupled to a facsimile unit via an interface device for transmission and receipt... |
| US-6,105,120 |
Method for implementing multiple format addressing in an embedded
microcontroller, a compiler being arranged... Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for... |
| US-6,105,119 |
Data transfer circuitry, DSP wrapper circuitry and improved processor
devices, methods and systems An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block... |
| US-6,105,118 |
System and method for selecting which data copy to read in an
information handling system The invention is a system, method, and computer readable medium for determining which copy of data to access in an information handling system. Since the same... |
| US-6,105,117 |
Source oriented data block relocation methodology and applications An apparatus is equipped with a source oriented data move technique. In one embodiment, the apparatus is a computer system and the source oriented data moving... |
| US-6,105,116 |
Method and apparatus of controlling a disk cache during a degenerated
mode of operation A disk cache is controlled to continue duel data writing even during a degenerated mode of operation due to a failure of a cache memory, and also to continue a... |
| US-6,105,115 |
Method and apparatus for managing a memory array A NRU algorithm is used to track lines in each region of a memory array such that the corresponding NRU bits are reset on a region-by-region basis. That is, the... |
| US-6,105,114 |
Two-dimensional array transposition circuit reading two-dimensional
array in an order different from that for... A two-dimensional array transposition circuit having a small circuit scale and accordingly having a small power consumption includes a memory cell array capable... |
| US-6,105,113 |
System and method for maintaining translation look-aside buffer (TLB)
consistency A system and method for maintaining consistency between translational look-aside buffers (TLB) and page tables. A TLB has a TLB table for storing a list of... |
| US-6,105,112 |
Dynamic folding of cache operations for multiple coherency-size systems A method is disclosed of managing architectural operations in a computer system whose architecture includes components having varying coherency granule sizes. A... |
| US-6,105,111 |
Method and apparatus for providing a cache management technique A cache technique for maximizing cache efficiency by assigning ages to elements which access the cache, is described. In one embodiment, the cache technique... |
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