Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-6,198,707 |
Optical disc apparatus capable of multiple write sessions in a single track An optical disc apparatus includes a pause circuit for pausing data encoders upon receiving a pause signal so that a write operation may be paused without... |
| US-6,198,706 |
Optical format compatible recording and/or playback device The invention relates to a method and an arrangement for a compatible recording and/or reproduction device for the reproduction of information from, and/or for... |
| US-6,198,705 |
Error-tolerant target-sector search using previous N sector ID for
high-speed CD An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the... |
| US-6,198,704 |
Magneto-optical recording medium A magneto-optical recording medium from which data is read by using a Kerr effect and which is capable of preventing signal imbalance caused from change in... |
| US-6,198,702 |
Information providing and collecting apparatus and recording medium An information providing and collecting apparatus includes an information dividing circuit and an adding means. The information dividing circuit divides an input... |
| US-6,198,701 |
Electrochemical timer An electrochemical timer is described that is compact, lightweight, inexpensive to manufacture, and simple to use in which the consumption of reactive materials... |
| US-6,198,700 |
Method and apparatus for retiming test signals A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first... |
| US-6,198,699 |
Semiconductor testing apparatus An IC testing apparatus which is able to measure the execution time of an automatic function for each DUT by a one-time test, and to grade said automatic... |
| US-6,198,698 |
Illuminating, visual, time indicating device An illuminating, visual, time indicating device, incorporating a new and innovative time telling indication means that is both functional and stylistic. The... |
| US-6,198,697 |
Watch case fitted with control means A watch case (1) including a wall (6) with an outer face and an inner face, which defines a housing intended to accommodate a watch movement (7), and control... |
| US-6,198,696 |
Device and method for tracking time zone changes in communications devices A portable processing device, such as a laptop computer, includes a time-of-day clock that is dynamically adjusted based upon occurrences of travel among... |
| US-6,198,695 |
Event monitoring device This disclosure relates to a method of monitoring patent compliance using a multiple step event acknowledgment process. a) programming a device with event times and... |
| US-6,198,694 |
Method and device for projectile measurements According to a method and a device for deciding relative to a chosen reference system, and without contact, the position, direction or speed--or any combination... |
| US-6,198,693 |
System and method for finding the direction of a wave source using an array
of sensors A system and method for finding the direction of a wave source using an array of sensors. The system includes a sensor array for measuring waves from the wave... |
| US-6,198,692 |
Apparatus suitable for searching objects in water A fish finder having two 1D transducer arrays vertically arranged on a ship's hull. Each 1D transducer array provides a beam having a narrow width on a plane... |
| US-6,198,691 |
Force page paging scheme for microcontrollers of various sizes using data
random access memory A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory... |
| US-6,198,690 |
Clock control circuit with an input stop circuit A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse... |
| US-6,198,689 |
Integrated circuit device with built-in self timing control circuit The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted... |
| US-6,198,688 |
Interface for synchronous semiconductor memories Various techniques and novel architectures for synchronous memories that improve the overall speed and bandwidth of the memory circuit. In one embodiment, two... |
| US-6,198,687 |
Semiconductor memory device having a plurality of transfer gates and
improved word line and column select... A semiconductor memory device which receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from an external device. The device... |
| US-6,198,686 |
Memory device having row decoder On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit... |
| US-6,198,685 |
Word-line driving circuit and semiconductor memory device There is provided a word-line driving circuit has: two P-channel type transistors which are connected in a flip-flop configuration and one of which is connected... |
| US-6,198,684 |
Word line decoder for dual-port cache memory In one embodiment, a memory cell having a first port and a second port is provided. A first word line is associated with the first port, and a second word line... |
| US-6,198,683 |
Memory device A memory device comprising: a step-down voltage generating circuit for generating a first step-down voltage by stepping down a power-supply voltage, and a second... |
| US-6,198,682 |
Hierarchical dynamic memory array architecture using read amplifiers
separate from bit line sense amplifiers A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared... |
| US-6,198,681 |
Sense amplifier for low voltage memory arrays A sense amplifier is coupled to a memory array comprising a first plurality of cells coupled to a first bit line and a dummy cell coupled to a second bit line.... |
| US-6,198,680 |
Circuit for resetting a pair of data buses of a semiconductor memory device A semiconductor memory, such as an SDRAM, includes a data bus pair, a first reset circuit, a second reset circuit and a control circuit. The first reset circuit... |
| US-6,198,679 |
Semiconductor memory device The objective of the invention is to read and write data in synchronization with a high-speed clock signal. The pulse width of the timing control signal (FY... |
| US-6,198,678 |
Semiconductor memories A semiconductor memory, for example of the ROM type, has columns of memory cells with a bitline for each column connected to the cells of the column. The... |
| US-6,198,677 |
Boosted sensing ground circuit A new noise control circuit which connects the sense ground node to ground in two specific period of times so that the NSA bouncing is minimized. Preferably... |
| US-6,198,676 |
Test device As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory... |
| US-6,198,675 |
RAM configurable redundancy A circuit and method for replacing a defective memory line with a usable memory line. A test is carried out to locate any defective lines, whether a row line or... |
| US-6,198,674 |
Data strobe signal generator of semiconductor device using toggled pull-up
and pull-down signals Disclosed is a data strobe signal generator of the SDRAM device. The data strobe signal generator according to the present invention does not have to use a... |
| US-6,198,673 |
Semiconductor integrated circuit having a unit cell including NMOS and PMOS
transistors A semiconductor integrated circuit having a core region and an I/O region includes a clock signal line for transferring a clock signal, basic unit cells and... |
| US-6,198,672 |
Voltage phase generator with increased driving capacity A voltage phase generator that generates a normal voltage phase, a negated normal voltage phase, a boosted voltage phase, and a negated boosted voltage phase.... |
| US-6,198,671 |
Semiconductor memory device The semiconductor memory device formed on a semiconductor substrate includes: a memory cell array having a plurality of memory cells formed at intersections... |
| US-6,198,670 |
Bias generator for a four transistor load less memory cell The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the... |
| US-6,198,669 |
Semiconductor integrated circuit A semiconductor integrated circuit includes an incorporated memory unit, a first register unit for storing data to be written in the memory unit as a test... |
| US-6,198,668 |
Memory cell array for performing a comparison A memory cell having a memory cell state is disclosed. The memory cell state includes a memory unit configured to store a bit of data wherein the bit of data... |
| US-6,198,667 |
Plural memory banks device that can simultaneously read from or write to
all of the memory banks during testing A semiconductor memory apparatus having a multi-bank memory array and data input/output method are disclosed. A plurality of memory banks are row-accessed at one... |
| US-6,198,666 |
Control input timing-independent dynamic multiplexer circuit An output MUX for a high speed memory is provided with an interlock circuit to insure that only one data bit can be on the output line at a given time. A... |
| US-6,198,665 |
One chip semiconductor integrated circuit device having two modes of data
write operation and bits setting... A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for... |
| US-6,198,664 |
APDE scheme for flash memory application A method for erasing a flash EEPROM device that includes a plurality of memory cells. The plurality of memory cells is erase verified and an erase pulse is... |
| US-6,198,663 |
Non-volatile semiconductor memory IC A non-volatile semiconductor memory IC has both a flash memory and a CPU mounted thereon. The CPU is provided with a ROM which stores a program code and a memory... |
| US-6,198,662 |
Circuit and method for pre-erasing/erasing flash memory array A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge... |
| US-6,198,661 |
Sensing circuit for semiconductor device and sensing method using the same Sensing circuit for a semiconductor device and a sensing method using the same which allows sensing of a selected nonvolatile memory cell at a low voltage, a low... |
| US-6,198,660 |
Synchronous multilevel non-volatile memory and related reading method The memory and method for reading include a synchronous multilevel non-volatile memory with cell addresses which define a pair of memory cells on different... |
| US-6,198,659 |
Defective address data storage circuit for nonvolatile semiconductor memory
device having redundant function... In a defective address data storage circuit for a nonvolatile semiconductor memory, electrically erasable programmable memory cells are arranged in rows and... |
| US-6,198,658 |
High density flash memory architecture with columnar substrate coding Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the... |
| US-6,198,657 |
Nonvolatile semiconductor memory device and method of manufacturing the
same A nonvolatile memory device is provided capable of shipping after setting it as a flash memory or as a one-time memory, and which cannot be altered to a flash... |
Copyright 2008−2012 Patents.com
