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| Patent # | Description |
|---|---|
| US-6,198,356 |
Voltage controlled oscillator power supply and temperature compensation
circuit Circuits such as Phase Lock Loops which use VCO's are affected by temperature and power supply variations which effect the performance of the circuit,... |
| US-6,198,355 |
Dual edge-triggered phase detector and phase locked loop using same There is disclosed a phase detector which triggers on both rising and falling edges of an input pulse signal. This effectively doubles the frequency of the input... |
| US-6,198,354 |
System for limiting if variation in phase locked loops An apparatus for limiting intermediate frequency variation in a multiple conversion phase locked loop includes a reference oscillator and a voltage controlled... |
| US-6,198,353 |
Phase locked loop having direct digital synthesizer dividers and improved
phase detector A digital phase locked loop (PLL) frequency synthesizer having the conventional voltage controlled oscillator (VCO) divider in the feedback loop to the phase... |
| US-6,198,352 |
Radio frequency low noise amplifier fabricated in complementary metal oxide
semiconductor technology The low noise amplifier (LNA) of the present invention comprises an input stage including an input inductor and an input circuit portion. The input circuit... |
| US-6,198,351 |
Power sensing apparatus for power amplifiers In a power amplifier comprising a plurality of cascaded field effect transistors (FETs), a power sensing circuit for sensing the output power of the power... |
| US-6,198,350 |
Signal amplifier with fast recovery time response, efficient output driver
and DC offset cancellation capability A signal amplifying circuit (24) includes level shifting input circuits (D1-D4) permitting input common-mode voltages (VIN1 and VIN2) of an amplifier and fault... |
| US-6,198,349 |
Variable gain amplifier having a maximum attenuation-factor limiting
resistor A variable gain amplifier has a large variable range of a gain with respect to an analog signal having a level changing at a high-speed. The variable gain... |
| US-6,198,348 |
Differential circuit with reverse isolation A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that... |
| US-6,198,347 |
Driving circuits for switch mode RF power amplifiers The present invention, generally speaking, provides an RF amplifier circuit architecture that enables high efficiency to be achieved while avoiding complicated... |
| US-6,198,346 |
Adaptive linear amplifier without output power loss A multi-tone signal amplifier topology and an amplifying method in which a first amplifier outputs a first signal having at least one fundamental frequency... |
| US-6,198,345 |
Error reduction in quadrature polyphase filters with low open loop gain
operational amplifiers A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that... |
| US-6,198,344 |
Back bias voltage level sensing circuit A back bias voltage level sensing circuit includes a constant current generation unit for generating a constant current regardless of a variation in a power... |
| US-6,198,343 |
Current mirror circuit The current mirror circuit in accordance with the present invention includes a first current mirror circuit composed of first and second MOS transistors being... |
| US-6,198,342 |
Charge pump circuit simple in construction and free from trouble even at
low voltage In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which... |
| US-6,198,341 |
Substrate bias voltage generating circuit for use in a semiconductor device A circuit is provided for biasing a semiconductor substrate. The circuit comprises a driving signal generating circuit and a charge pump circuit. The driving... |
| US-6,198,340 |
High efficiency CMOS pump circuit In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are... |
| US-6,198,339 |
CVF current reference with standby mode A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency. |
| US-6,198,338 |
Method of constructing a fuse for a semiconductor device and circuit using
same A method for providing a fuse apparatus for a semiconductor device includes providing at least one fuse portion of the fuse apparatus with at least two fuses... |
| US-6,198,337 |
Semiconductor device for outputting a reference voltage, a crystal
oscillator device comprising the same, and a... A semiconductor device for outputting a reference voltage, the value of which changes depending on the ambient temperature, and a crystal oscillator device... |
| US-6,198,336 |
Threshold element A threshold element enabling a logical operation with fewer transistors and easy design and setting of an element weight and a threshold value is provided. In a... |
| US-6,198,335 |
Method and apparatus to drive the coil of a magnetic write head A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An... |
| US-6,198,334 |
CMOS circuit In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching... |
| US-6,198,333 |
Analog multiplier with thermally compensated gain A bipolar analog multiplier with a greatly reduced output sensitivity to temperature. The multiplier uses the difference between the multiplier input voltages... |
| US-6,198,332 |
Frequency doubler and method of doubling frequency A frequency doubler includes a first Gilbert cell, a second Gilbert cell coupled to the first Gilbert cell, a frequency generator configured to apply a first... |
| US-6,198,331 |
Voltage level converter circuit improved in operation reliability A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected... |
| US-6,198,330 |
Adaptive-load inverters and methods Inverters are provided which adapt their output impedance to the driven load and thereby enhance inverter performance (e.g., current drive, switching speed and... |
| US-6,198,329 |
Auto zero circuitry and associated method A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage... |
| US-6,198,328 |
Circuit configuration for producing complementary signals The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a... |
| US-6,198,327 |
Pulse generator with improved high speed performance for generating a
constant pulse width ON-OFF operations of the pull-up and pull-down transistors are independently controlled so as to generate a start edge of a pulse signal in synchronizing with... |
| US-6,198,326 |
Delay time compensation circuit for clock buffer A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which... |
| US-6,198,325 |
Differencing non-overlapped dual-output amplifier circuit An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital... |
| US-6,198,324 |
Flip flops Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output... |
| US-6,198,323 |
Flip-flop having gated inverter feedback structure with embedded
preset/clear logic A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage... |
| US-6,198,322 |
Duty-ratio correction circuit and clock generation circuit A duty ratio can be corrected to 1:1 without affecting the operation of a PLL or DLL circuit. A rising-edge control circuit (1a) generates a signal (S10) by... |
| US-6,198,321 |
Device for the generation of a drive signal phase-shifted with respect to
an external synchronization A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give... |
| US-6,198,320 |
Differential charge pump and filter with common-mode voltage control A charge pump and filter for a phase-lock loop circuit are provided with common-mode voltage control for differential outputs to be used by a voltage-controlled... |
| US-6,198,319 |
Power-on circuit built in IC The invention provides a power-on circuit which assures a high impedance state of a terminal of an IC until the IC starts its operation after a point of time... |
| US-6,198,318 |
Power-on-reset circuit An apparatus is used to control a reset function of an electronic device. The apparatus includes a circuit adapted to monitor a system voltage level and deliver... |
| US-6,198,317 |
Frequency multiplication circuit An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle... |
| US-6,198,316 |
CMOS off-chip driver circuit An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and... |
| US-6,198,315 |
Current detection circuit A current detection circuit having a voltage conversion section for converting current flowing to a load to a voltage; an amplifier section having an operational... |
| US-6,198,314 |
Sample and hold circuit and method therefor A sample and hold circuit (200) accepts an input (202). During a first half of the clock (204) (either an active high portion or an active low portion) the... |
| US-6,198,313 |
Infinite sample-and-hold circuit An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects... |
| US-6,198,312 |
Low level input voltage comparator A circuit and a method for comparing an input voltage to an internally generated reference voltage utilize a bias network to make the voltage comparison. The... |
| US-6,198,311 |
Expandable analog current sorter based on magnitude A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents... |
| US-6,198,310 |
Circuit arrangement for monitoring a clock-timed load A circuit arrangement for monitoring a load operated with a clock signal is provided. The circuit arrangement may be applied to the field of automotive... |
| US-6,198,309 |
Emitter follower output with programmable current An integrated circuit device having emitter follower outputs with adjustable output currents includes a variable bias generator that produces a bias voltage. The... |
| US-6,198,308 |
Circuit for dynamic switching of a buffer threshold A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters designed with different skewed threshold... |
| US-6,198,307 |
Output driver circuit with well-controlled output impedance An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The... |
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