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| Patent # | Description |
|---|---|
| US-6,199,157 |
System, method and medium for managing information A system, method and medium for configuring an item such as a machine having multiple optional components is provided. This is accomplished using "options,"... |
| US-6,199,156 |
System for explicitly referencing a register for its current content when
performing processor context switch In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a... |
| US-6,199,155 |
Data processor A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines... |
| US-6,199,154 |
Selecting cache to fetch in multi-level cache system based on fetch address
source and pre-fetching additional... A processor employs a first instruction cache, a second instruction cache, and a fetch unit employing a fetch/prefetch method among the first and second... |
| US-6,199,153 |
Method and apparatus for minimizing pincount needed by external memory
control chip for multiprocessors with... A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to... |
| US-6,199,152 |
Translated memory protection apparatus for an advanced microprocessor A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a... |
| US-6,199,151 |
Apparatus and method for storing a device row indicator for use in a
subsequent page-miss memory cycle An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage... |
| US-6,199,150 |
Data memory apparatus forming memory map having areas with different access
speeds A data memory apparatus includes at least one memory device forming a memory map including at least a first memory area and a second memory area; and an access... |
| US-6,199,149 |
Overlay counter for accelerated graphics port A method for controlling processing of overlay requests is disclosed. The method comprises the step of disabling an overlay request to a memory. The overlay... |
| US-6,199,148 |
Method and apparatus for preventing unauthorized use in systems having
alternative control for avoiding defect... A method of preventing unauthorized use includes defining a first original medium ID information stored in a predetermined order which indicates a location of... |
| US-6,199,147 |
Distributed-memory multiprocessor computer system with directory-based
cache coherency with ambiguous mappings... A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in... |
| US-6,199,146 |
Storage management system and method for increasing capacity utilization of
nonvolatile storage devices using... A system and method for increasing capacity utilization of non-volatile storage devices within a group of non-volatile storage devices used to store data from at... |
| US-6,199,145 |
Configurable page closing method and apparatus for multi-port host bridges A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a... |
| US-6,199,144 |
Method and apparatus for transferring data in a computer system A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and,... |
| US-6,199,143 |
Computing system with fast data transfer of CPU state related information A method and apparatus in a computer system selectively stores CPU state related information in parallel in a first and a second set of registers. The two sets... |
| US-6,199,142 |
Processor/memory device with integrated CPU, main memory, and full width
cache and associated method An integrated processor/memory device comprising a main memory, a CPU, and a full width cache. The main memory comprises main memory banks. Each of the main... |
| US-6,199,141 |
Method and apparatus for virtual memory mapping and transaction management
in an object-oriented database system An apparatus and method are provided for virtual memory mapping and transaction management in an object-oriented database system having permanent storage for... |
| US-6,199,140 |
Multiport content addressable memory device and timing signals A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1)... |
| US-6,199,139 |
Refresh period control apparatus and method, and computer The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful... |
| US-6,199,138 |
Controlling a paging policy based on a requestor characteristic A memory access control technique includes receiving a memory access request indication, performing a memory access operation in accordance with the memory... |
| US-6,199,137 |
Method and device for controlling data flow through an IO controller An IO controller device and method for controlling data flow, the method including determining a desired configuration for the IO controller, reprogramming the... |
| US-6,199,136 |
Method and apparatus for a low data-rate network to be represented on and
controllable by high data-rate home... A PC-based home automation system uses a low data-rate transport layer and COM-based software components for control of devices in a home automation network. The... |
| US-6,199,135 |
Source synchronous transfer scheme for a high speed memory interface Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by... |
| US-6,199,134 |
Computer system with bridge logic that asserts a system management
interrupt signal when an address is made to... A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge... |
| US-6,199,133 |
Management communication bus for networking devices A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at... |
| US-6,199,132 |
Communication link with isochronous and asynchronous priority modes A bus transfers information including isochronous and asynchronous data between a first and a second integrated circuit. The bus guarantees a minimum bandwidth... |
| US-6,199,131 |
Computer system employing optimized delayed transaction arbitration
technique A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit... |
| US-6,199,130 |
Concurrent maintenance for PCI based DASD subsystem with concurrent
maintenance message being communicated... In an electrical system, concurrent maintenance of a system component coupled to the system by an adapter on a first communications path is accomplished through... |
| US-6,199,129 |
Bus segment or bus interface for connection of a subassembly of a
programmable controller to a bus In order, in the case of a programmable logic controller having a modular structure, to be able to insert and withdraw assemblies even in the course of... |
| US-6,199,128 |
Smart card system for use with peripheral devices A smart card that is compatible with multiple different protocols includes a standard set of contacts that comply with the protocols of a published standard, and... |
| US-6,199,127 |
Method and apparatus for throttling high priority memory accesses A method and apparatus for throttling high priority memory accesses. An apparatus of the present invention includes an arbiter circuit and a throttling circuit.... |
| US-6,199,126 |
Processor transparent on-the-fly instruction stream decompression An apparatus and method for transparent on-the-fly decompression of the program instruction stream of a processor. Connected between a processor and a memory... |
| US-6,199,125 |
Input manager for a computer application with display icons mapped to a
user selectable set of standard... An input manager operating on a computer system is disclosed. The computer system includes a processor, a display, an application running on the processor and... |
| US-6,199,124 |
Arbitration system based on requester class and relative priority including
transmit descriptor valid bit for a... In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a... |
| US-6,199,123 |
Computer system for supporting increased PCI master devices without the
requiring additional bridge chips A PCI-based computer system is provided with an expanded number of PCI master devices, in effect a second level of PCI arbitration. The expansion is made... |
| US-6,199,122 |
Computer system, external storage, converter system, and recording medium
for converting a serial command and... In order to access a memory card of the ATA specification, a computer generates a command based on the USB. A conversion controller in a reader/writer receives... |
| US-6,199,121 |
High speed dynamic chaining of DMA operations without suspending a DMA
controller or incurring race conditions A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended... |
| US-6,199,120 |
IC card reading/writing apparatus and method for allowing use of multiple
vendors An IC card includes a card body, a memory section buried inside the card body and adapted to store data information and control information, and an interface... |
| US-6,199,119 |
Method and apparatus for the addition and removal of nodes from a common
interconnect An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured... |
| US-6,199,118 |
System and method for aligning an initial cache line of data read from an
input/output device by a central... A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked... |
| US-6,199,117 |
Generalized control for starting of tasks (processes and threads) A generalized applications programming interface (API) is inserted as a separate level above the API's of the operating system in a data processing system and... |
| US-6,199,116 |
Method and system for managing data while sharing application programs A method and system for managing data (i.e., objects) that are shared by multiple instances of a shared application program. A shared application program is an... |
| US-6,199,115 |
Attachment integrated claims system and operating method therefor An attachment integrated claims (AIC) system includes an e-mail form (with specific fields that must be filled out) that adjusts itself, in both information... |
| US-6,199,114 |
Initiating a user session at an internet terminal using a smart card Initiating a user session at an internet terminal using a smart card is provided. An internet terminal is coupled to a server system. The internet terminal... |
| US-6,199,113 |
Apparatus and method for providing trusted network security A session key is established for accessing a trusted network from a browser. An authentication process receives identification information from a user at the... |
| US-6,199,112 |
System and method for resolving fibre channel device addresses on a network
using the device's fully qualified... A method and system for discovering the location of a storage router, and therefore the attached storage devices, in a fibre channel network using the storage... |
| US-6,199,111 |
Client-led network computing system and its method In a distributed client-server system a client is connected to an arbitrary server using a communication module common to a plurality of servers and it uses... |
| US-6,199,110 |
Planned session termination for clients accessing a resource through a
server A method and apparatus are provided for passing a client from a first server to which the client was connected for accessing a resource, to a second server for... |
| US-6,199,109 |
Transparent proxying of event forwarding discriminators A method and system for processing an event notification generated by a proxy managed object in a management system, where the management system includes at... |
| US-6,199,108 |
Simplified setting up of a network of server computers preloaded with all
computer programs required by a group... A system is provided for setting up what is in effect a "plug and play" local area network for small businesses comprising a server computer and a plurality of... |
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