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| Patent # | Description |
|---|---|
| US-6,243,313 |
Semiconductor memory device, nonvolatile semiconductor memory device, and
their data reading method In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in... |
| US-6,243,312 |
Semiconductor memory device A semiconductor memory device feeds back a signal made by detecting a data sensing when reading a memory chip, precharges a local data bus within a short time,... |
| US-6,243,311 |
Digit line architecture for dynamic memory A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded... |
| US-6,243,310 |
Circuit and method for automatically regulating the equalization duration
when reading a nonvolatile memory An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input... |
| US-6,243,309 |
Semiconductor memory device having parallel test mode for simultaneously
testing multiple memory cells A semiconductor memory device having a parallel test mode for simultaneously testing a plurality of memory cells, comprising: a memory cell array having N... |
| US-6,243,308 |
Method for testing dynamic random access memory under wafer-level-burn-in In accordance with the present invention, a method is provided for testing dynamic random access memory under wafer-level-burn-in that substantially can overcome... |
| US-6,243,307 |
Semiconductor device including tester circuit suppressible of circuit scale
increase and testing device of... After writing data into a memory cell array according to an internal address signal, data read out from each memory cell is compared with expected value data in... |
| US-6,243,306 |
Defect management engine for generating a unified address to access memory
cells in a primary and a redundancy... A method and apparatus for eliminating defects present in memory devices by way of a defect management engine (DME) is described. The DME integrates a plurality... |
| US-6,243,305 |
Memory redundancy device and method A redundant circuit and method for a semiconductor memory device is disclosed. The redundant circuit includes a programmable circuit for selectively generating... |
| US-6,243,304 |
Sample and load scheme for observability internal nodes in a PLD A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides... |
| US-6,243,303 |
Method and circuitry for writing data A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second... |
| US-6,243,302 |
Apparatus for outputting data using common pull-up/pull-down lines with
reduced load A synchronous memory device includes: a plurality of pipelatch circuits storing data as pull-up and pull-down signals, transferring the stored data to pull-up... |
| US-6,243,301 |
Semiconductor memory device and signal line switching circuit Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing... |
| US-6,243,300 |
Substrate hole injection for neutralizing spillover charge generated during
programming of a non-volatile... A method of erasing a memory cell that includes a first region and a second region with a channel therebetween that has spillover electrons and a gate above the... |
| US-6,243,299 |
Flash memory system having fast erase operation A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with... |
| US-6,243,298 |
Non-volatile memory cell capable of being programmed and erased through
substantially separate areas of one of... In accordance with the present invention, a low VCC operational non-volatile memory cell includes a drain region and a source region separated by a channel... |
| US-6,243,297 |
Semiconductor storage device When a data write into a memory cell 11 is completed and a reset signal RST is set to level "H," a control voltage MCD output by a write control circuit 30 is... |
| US-6,243,296 |
Compact electrically erasable memory cells and arrays A nonvolatile memory cell (600) has a read device (510), program device (515), and tunnel diode (535). A write control line (WC) is directly coupled to the... |
| US-6,243,295 |
Nonvolatile semiconductor memory A memory cell in a NAND cell unit is constructed by a main transistor and parasitic transistor, which share a floating gate electrode and control gate electrode,... |
| US-6,243,294 |
Memory architecture for non-volatile storage using gate breakdown structure
in standard sub 0.35 micron process A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is... |
| US-6,243,293 |
Contacted cell array configuration for erasable and programmable
semiconductor memories A contacted array of programmable and erasable semiconductor memory devices. Each of the memory devices has a split gate structure, including a source region, a... |
| US-6,243,292 |
Nonvolatile semiconductor memory device capable of reducing memory array
area A memory cell array is divided into a plurality of memory cell blocks each collectively subjected to an erasing operation as a unit. A P well regions for memory... |
| US-6,243,291 |
Two-stage pipeline sensing for page mode flash memory A method for operating a page mode memory device includes decoding an address defining a page for access and sensing first data on a first portion of the page.... |
| US-6,243,290 |
Nonvolatile semiconductor memory device The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel... |
| US-6,243,289 |
Dual floating gate programmable read only memory cell structure and method
for its fabrication and operation A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control... |
| US-6,243,288 |
Giant magnetoresistive sensor, thin-film read/write head and magnetic
recording apparatus using the sensor A giant magnetoresistive sensor which is improved in reproduction output and peak asymmetry of read-back waveform. It is composed of a first free ferromagnetic... |
| US-6,243,287 |
Distributed decode system and method for improving static random access
memory (SRAM) density A static random access memory (SRAM) cell is provided that optimizes the density of memory cells in an array with the maximum speed possible in addressing the... |
| US-6,243,286 |
Semiconductor memory device and method of fabricating the same An SRAM comprises first, second and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver... |
| US-6,243,285 |
ROM-embedded-DRAM A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower... |
| US-6,243,284 |
Multivalued mask read-only memory A multivalued mask ROM is configured by arranging cell transistors in a matrix form, which is defined by wiring word lines and ground lines in rows and by wiring... |
| US-6,243,283 |
Impedance control using fuses A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to... |
| US-6,243,282 |
Apparatus for on-board programming of serial EEPROMs A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after complet assembly of the... |
| US-6,243,281 |
Method and apparatus for accessing a segment of CAM cells in an intra-row
configurable CAM system A method and apparatus for accessing a segment of CAM cells in an intra-row configurable CAM system. For one embodiment, the CAM system includes a CAM array and... |
| US-6,243,280 |
Selective match line pre-charging in a partitioned content addressable
memory array Rows of a CAM array are partitioned into a plurality of row segments, with each row segment having a corresponding match line segment. A first match line segment... |
| US-6,243,279 |
Semiconductor integrated circuit device A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a... |
| US-6,243,278 |
Drive circuit for synchronous rectifier and method of operating the same A drive circuit for driving a rectifier switch, a method of driving the rectifier switch and a power converter employing the drive circuit or the method. In one... |
| US-6,243,277 |
Bi-directional dc to dc converter for energy storage applications A bi-directional energy storage module and method of operation is disclosed. The converter includes an inductive component, an energy storage element, two diodes... |
| US-6,243,276 |
Power supply system for battery operated devices A power supply converts an AC input voltage to a DC output voltage and supplies the DC output voltage to power devices. The power supply includes a housing, a... |
| US-6,243,275 |
Dc to dc power converter using synchronously switched switches A full bridge and half bridge dc-dc converter including a primary side having switching devices connected to a transformer, and a primary side controller, a... |
| US-6,243,274 |
Shields for electronic components with ready access to shielded components A plurality of shields is provided for shielding selected electronic components and electronic sub-assemblies mounted on a printed wiring board assembly from... |
| US-6,243,273 |
Mini-backplane "T" assembly Apparatus for mounting retrofit equipment modules into the equipment mounting cabinetry of an installed modular equipment signal network includes an interface... |
| US-6,243,272 |
Method and apparatus for interconnecting multiple devices on a circuit
board A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling... |
| US-6,243,271 |
Positioner for positioning an electronic card in a slot A positioner for an electronic card in a slot, the positioner including a head and at least one leg, the height of the positioner being substantially equal to... |
| US-6,243,270 |
Method and apparatus for attaching a printed circuit board to a chassis A printed circuit board (PCB) includes a plurality of electronic devices electrically coupled together and disposed on a first side of the PCB. The PCB also... |
| US-6,243,269 |
Centralized cooling interconnect for electronic packages An apparatus for centralizing heat dissipation on printed circuit boards is disclosed. The printed circuit board materials are used to thermally conduct heat... |
| US-6,243,268 |
Cooled IC chip modules with an insulated circuit board A cooling assembly for an integrated circuit chip module wherein an evaporator-cooled IC module mounted on a printed circuit board is enclosed within an... |
| US-6,243,267 |
PGA socket with a heat sink fastening device A PGA socket comprises a base, a cover slidably attached to the base, a lever and a slider. The lever is rotatablely coupled between the base and the cover to... |
| US-6,243,266 |
Locking device for CPU packages of different thicknesses A locking device comprises a number of pegs and a bracket for securely locking a heat sink to CPU packages of a range of thicknesses. The pegs each have a cap... |
| US-6,243,265 |
Processor EMI shielding A heat sink retention module provides physical support for a heat sink while providing an electrical ground path for the heat sink. The retention module includes... |
| US-6,243,264 |
SRAM heat sink assembly and method of assembling A heat sink assembly includes a heat sink, a circuit board and an integrated circuit package. The package is located between the heat sink and the circuit board... |
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