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| Patent # | Description |
|---|---|
| US-6,242,963 |
Differential mixer with improved linearity A mixing apparatus includes a Gilbert cell connected to a first load and a second load. In one embodiment each load contains transistors that are configured as a... |
| US-6,242,962 |
Level shift circuit having plural level shift stage stepwise changing
potential range without applying large... A level shift circuit has plural level shift stages connected in series between an input node and an output node for producing an output signal, and a first... |
| US-6,242,961 |
Methods and circuits for restoration of a drooped DC signal Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the... |
| US-6,242,960 |
Internal clock signal generating circuit employing pulse generator The internal clock signal generating circuit of the present invention includes a pulse generation circuit for receiving a reference clock signal which is... |
| US-6,242,959 |
Programmable delay circuit and method with dummy circuit compensation One or more main programmed delay circuits (PDCs) are compensated to provide constant delays despite variations in environmental factors, such as temperature and... |
| US-6,242,958 |
Master slave flip flop as a dynamic latch A flip-flop circuit comprising a dynamic master coupled to a clock, the clock being characterized by an active stated of a limited duration, and a static latch... |
| US-6,242,957 |
Master-slave type flip-flop According to one embodiment, a master-slave flip-flip circuit (MS-FF) (100) includes master input transfer gate (108) connected to the input of a master latch... |
| US-6,242,956 |
Phase locked loop A hybrid phase locked loop employs both analog and digital circuitry. A digital to analog converter (DAC) provides a current output signal in conjunction with a... |
| US-6,242,955 |
Delay lock loop circuit, system and method for synchronizing a reference
signal with an output signal A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog... |
| US-6,242,954 |
Timing clock generation circuit using hierarchical DLL circuit The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase... |
| US-6,242,953 |
Multiplexed synchronization circuits for switching frequency synthesized
signals Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock... |
| US-6,242,952 |
Inverting hold time latch circuits, systems, and methods A domino logic circuit (18) comprising a first phase domino logic circuit (20) operable in a precharge phase and an evaluate phase. The first phase domino logic... |
| US-6,242,951 |
Adiabatic charging logic circuit An adiabatic charging logic circuit includes a logic circuit and a power supply section. The logic circuit is constituted by a plurality of logic elements. The... |
| US-6,242,950 |
Bidirectional data transfer path having increased bandwidth A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for... |
| US-6,242,949 |
Digital voltage translator and its method of operation A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and... |
| US-6,242,948 |
Semiconductor integrated circuit device A semiconductor integrated circuit device comprises a first switching element, such as a p-channel MOSFET, capable of connecting said first power supply with a... |
| US-6,242,947 |
PLD having a window pane architecture with segmented interconnect wiring
between logic block arrays A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes... |
| US-6,242,946 |
Embedded memory block with FIFO mode for programmable logic device An programmable logic device has an enhanced embedded array block for the efficient implementation of logic functions including a random access memory and a... |
| US-6,242,945 |
Field programmable gate array with mask programmable I/O drivers A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a... |
| US-6,242,944 |
Real-time reconfigurable vision computing system An image processing system uses an FPGA and an external memory to form neighborhoods for image processing. The FPGA is connected to the external memory in a way... |
| US-6,242,943 |
Programmable multi-standard I/O architecture for FPGAS The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing... |
| US-6,242,942 |
Integrated circuit output buffers having feedback switches therein for
reducing simultaneous switching noise... Integrated circuit output buffers include pull-down an pull-up circuits and a control circuit that utilizes a preferred feedback circuit to facilitate a... |
| US-6,242,941 |
Reducing I/O noise when leaving programming mode An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user... |
| US-6,242,940 |
Data input buffer circuit A data input buffer circuit is disclosed. This circuit includes a first basic circuit which includes a first NOR-gate for NORing a first control signal and a... |
| US-6,242,939 |
Superconducting circuit having superconductive circuit device of
voltage-type logic and superconductive circuit... A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the... |
| US-6,242,938 |
Electrical circuit to detect load current An electric circuit for determining the load current of a clocked load having at least one inductive component and being assigned a free-wheeling circuit has a... |
| US-6,242,937 |
Hot carrier measuring circuit A hot carrier measuring circuit of the present invention, which measures the characteristic degradation of a semiconductor device due to AC operation, includes a... |
| US-6,242,936 |
Circuit for driving conductive line and testing conductive line for current
leakage A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP)... |
| US-6,242,935 |
Interconnect for testing semiconductor components and method of fabrication An interconnect for testing semiconductor components contained on a substrate, such as dice on a wafer, or chip scale packages on a panel is provided. Also... |
| US-6,242,934 |
Background leakage zeroing by temperature and voltage dependence for IDDQ
measurement and defect resolution A method for detecting defects in a semiconductor device using IDDQ testing techniques that is not dependent upon the background leakage current for defect... |
| US-6,242,933 |
Device probe socket forming part of a test head, interfacing between test
head and a probe handler, used for... A new probe socket is provided that allows for high speed and dependable contacting of points of contact on the Device Under Test. The new probe socket is aimed... |
| US-6,242,932 |
Interposer for semiconductor components having contact balls An interposer for electrically engaging semiconductor components having contact balls is provided. In a testing embodiment, the interposer configures a test... |
| US-6,242,931 |
Flexible semiconductor interconnect fabricated by backside thinning An interconnect for testing semiconductor components includes a thinned substrate, and first contacts on the substrate for electrically engaging second contacts... |
| US-6,242,930 |
High-frequency probe capable of adjusting characteristic impedance in end
part and having the end part detachable In a high-frequency probe having a detachable end according to the present invention, parts relating to replacement of an end unit are three parts, that is, an... |
| US-6,242,929 |
Probe needle for vertical needle type probe card and fabrication thereof A probe needle for a vertical needle type probe card is obtained that allows testing of electrical characteristics to be carried at high accuracy and that has... |
| US-6,242,928 |
Method and apparatus for detecting resistance of oxygen concentration
sensor The resistance of an air-fuel-ratio sensor element is determined from current detected before changing an applied voltage to the sensor and current detected when... |
| US-6,242,927 |
Method and apparatus measuring parameters of material A method and apparatus for measuring at least one parameter of material are disclosed herein. The method includes generating multiple frequency signals having... |
| US-6,242,926 |
Method and apparatus for moving an article relative to and between a pair
of thickness measuring probes to... A method and apparatus for moving an article relative to and between a pair of distance sensing probes of a thickness measuring apparatus which are spaced apart... |
| US-6,242,925 |
EMI susceptibility testing apparatus and method Non-destructive EMI susceptibility testing involves near-field injection of very high levels of instantaneous energy and low average power through localized... |
| US-6,242,924 |
Method for electronically measuring size of internal void in electrically
conductive lead The size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging... |
| US-6,242,923 |
Method for detecting power plane-to-power plane shorts and I/O net-to power
plane shorts in modules and printed... A method of locating in a non-destructive and non-invasive manner power plane-to-power plane shorts or I/O net-to-power plane shorts found in a printed circuit... |
| US-6,242,922 |
Arc detection architecture based on correlation for circuit breakers A low cost mixed analog digital application specific integrated circuit (ASIC) includes a standard central processing it (CPU) programmed to execute a... |
| US-6,242,921 |
Alternator testing apparatus and method An alternator test apparatus includes a processor and solenoid drivers for controlling solenoids to selectively switch three discrete, fixed-resistance loads and... |
| US-6,242,920 |
Apparatus for use in a DMM for measuring the battery voltage of the DMM A circuit for use in a DMM utilizes an auxiliary A/D converter to measure the battery voltage of the DMM and displays the result on the LCD display screen of the... |
| US-6,242,919 |
Multi-probe MRI/MRT system A system for performing magnetic resonance imaging and magnetic resonance therapy and a method for operating the system. The system may include one or several... |
| US-6,242,918 |
Apparatus and method for reducing the recovery period of a probe in pulsed
nuclear quadrupole resonance and... A nuclear quadrupole resonance (NQR) or nuclear magnetic resonance (NMR) apparatus which includes a probe and a variable impedance spectrometer. The probe emits... |
| US-6,242,917 |
Magnetic resonance transmission antenna A magnetic resonance transmission antenna has at least two transmission elements that independently respectively generate a linearly polarized, discrete magnetic... |
| US-6,242,916 |
Partial fourier acquistion of MR data over a limited field of view and
image reconstruction Two incomplete k-space data sets are acquired with an MRI system using two surface coils. The data from the two surface coils is combined in a Sense process to... |
| US-6,242,915 |
Field-frequency lock system for magnetic resonance system A field-frequency lock system for an MRI system includes a microcoil and resonant sample located to sense changes in the polarizing magnetic field. Changes are... |
| US-6,242,914 |
Magnetic resonance imaging method and magnetic resonance imaging system A method and a system for magnetic resonance imaging using echo planar method enable obtaining MRI images reduced in ghost artifacts. The magnetic resonance... |
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