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| Patent # | Description |
|---|---|
| US-6,243,816 |
Single sign-on (SSO) mechanism personal key manager A method of managing passwords of users desiring access to multiple target resources in a computer enterprise environment. For each given user, each of a set of... |
| US-6,243,815 |
Method and apparatus for reconfiguring and managing firewalls and security
devices A method for reconfiguring network security devices coupled to a network directory services server, the network directory services server providing network... |
| US-6,243,814 |
Method and apparatus for reliable disk fencing in a multicomputer system A method and apparatus for fast and reliable fencing of resources such as shared disks on a networked system. For each new configuration of nodes and resources... |
| US-6,243,813 |
Method of detaching a security device from a personal computer A personal computer having a security function is provided. The computer includes an input/output device which inputs/outputs a password, a main memory which... |
| US-6,243,812 |
Authentication for secure devices with limited cryptography Authentication is provided for secure devices with limited cryptography, particularly for devices which do not have the capability to do public-key cryptography... |
| US-6,243,811 |
Method for updating secret shared data in a wireless communication system In the method for updating secret shared data (SSD) in a wireless communication system, a first party outputs a first random number as a first challenge wherein... |
| US-6,243,810 |
Method and apparatus for communicating a configuration sequence throughout
an integrated circuit chip A method and apparatus for communicating a configuration operation throughout an integrated circuit chip is disclosed. The present invention receives a... |
| US-6,243,809 |
Method of flash programming or reading a ROM of a computer system
independently of its operating system A computer system provides for flashing a non-volatile memory image to a non-volatile memory and reading data from a non-volatile memory independently of an... |
| US-6,243,808 |
Digital data bit order conversion using universal switch matrix comprising
rows of bit swapping selector groups An apparatus and method of performing random bit swapping including bit (single bit) swapping, nibble (4-bit) swapping, byte (8-bit) swapping, and half word... |
| US-6,243,807 |
Optimizing cache data load required for functions in loop routine by
sequentially collecting data in external... The performance of a computer architecture having cache memory is optimized by reorganizing the structure of information before such information is written into... |
| US-6,243,806 |
Program execution method and apparatus employing data flags for branching
determination A group of registers 26 consists of a plurality of general-purpose registers R0, R1, . . . . A flag is provided for each of these general-purpose registers. When... |
| US-6,243,805 |
Programming paradigm and microprocessor architecture for exact branch
targeting A microprocessor for executing exact branch targeting is disclosed. A microprocessor contains a fetch stage for fetching and receiving instructions from memory... |
| US-6,243,804 |
Single cycle transition pipeline processing using shadow registers A system and method for efficiently handling interrupts in a microcontroller environment is disclosed. An interrupt handling circuit preserves a current state of... |
| US-6,243,803 |
Method and apparatus for computing a packed absolute differences with
plurality of sign bits using SIMD add... A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of... |
| US-6,243,802 |
Apparatus and method for encrypted instructions Computer instructions are stored in a main memory in encrypted or coded form, e.g., to conserve memory space. The coded instructions are decoded prior to... |
| US-6,243,801 |
System with wait state registers A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a... |
| US-6,243,800 |
Computer The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch,... |
| US-6,243,799 |
Methods and apparatus for byte alignment operations for a memory device
that stores an odd number of bytes A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user... |
| US-6,243,798 |
Computer system for allowing a two word jump instruction to be executed in
the same number of cycles as a... A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor... |
| US-6,243,797 |
Multiplexed semiconductor data transfer arrangement with timing signal
generator A multiplexing arrangement for transferring data retrieved from a memory array to data outputs of a semiconductor memory, including a multiplexing circuit that... |
| US-6,243,796 |
Recording medium and recording or reproduction apparatus that provides
protection from unauthorized use of the... A recording-medium ID information, which is condition information read from the recording medium loaded into a recording and reproduction apparatus, is compared... |
| US-6,243,795 |
Redundant, asymmetrically parallel disk cache for a data storage system A data storage system includes redundant write caches, a disk controller and an array of disks. One of the redundant write caches is a primary write cache of RAM... |
| US-6,243,794 |
Data-processing system with CC-NUMA (cache-coherent, non-uniform memory
access) architecture and remote cache... A data-processing system with cc-NUMA architecture including a plurality of nodes each constituted by at least one processor intercommunicating with a ... |
| US-6,243,793 |
Protocol for arbitrating access to a shared memory area using historical
state information A method and apparatus for arbitrating access to a shared memory is disclosed. A memory marking unit in the shared memory is read to determine whether the shared... |
| US-6,243,792 |
Method and apparatus for identifying a least recently used item A method and apparatus for identifying a least recently used item of a set or group of items is disclosed. In accordance the method, a count value is associated... |
| US-6,243,791 |
Method and architecture for data coherency in set-associative caches
including heterogeneous cache sets having... A processor architecture and method are shown which involve a cache having heterogeneous cache sets. An address value of a data access request from a CPU is... |
| US-6,243,790 |
Methods and apparatus for re-arranging logical drives in a disk array
apparatus Modern disk array apparatus are capable of providing a plurality of logical disks within one cabinet. The present invention provides a disk array apparatus in... |
| US-6,243,789 |
Method and apparatus for executing a program stored in nonvolatile memory A method of executing a program includes the step of initiating execution of the program stored contiguously without code fragmentation in a nonvolatile memory.... |
| US-6,243,788 |
Cache architecture to enable accurate cache sensitivity A technique of monitoring the cache footprint of relevant threads on a given processor and its associated cache, thus enabling operating systems to perform... |
| US-6,243,787 |
Synchronization of interrupts with data pockets A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a... |
| US-6,243,786 |
Apparatus and method for generating an interrupt prohibited zone in
pipelined data processors In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special... |
| US-6,243,785 |
Hardware assisted polling for software drivers A method and system for programmably controlling hardware generation of interrupts by a peripheral component. In one embodiment, the present invention uses a... |
| US-6,243,784 |
Method and apparatus for providing precise circuit delays A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays... |
| US-6,243,783 |
Application programming interface for managing and automating data transfer
operations between applications... An applications programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure.... |
| US-6,243,782 |
Method and apparatus for disabling a graphics device when an upgrade device
is installed One embodiment of a graphics device that can be disabled when an upgrade graphics device is installed is described. The graphics device includes an interface to... |
| US-6,243,781 |
Avoiding deadlock by storing non-posted transactions in an auxiliary buffer
when performing posted and... In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head... |
| US-6,243,780 |
Interface of a monitor communicating with personal computer A monitor having a microcomputer for performing a serial peripheral interface (SPI) communication with a personal computer (PC) which can improve the... |
| US-6,243,779 |
Noise reduction system and method for reducing switching noise in an
interface to a large width bus A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity... |
| US-6,243,778 |
Transaction interface for a data communication system A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from... |
| US-6,243,777 |
Circuit for preventing bus contention A circuit for controlling the data transmissions among two devices capable of transmitting information, via an output buffer, over a bus, so as to prevent bus... |
| US-6,243,776 |
Selectable differential or single-ended mode bus A bus may be configured as either a single-ended mode bus or as a differential mode bus, depending on the system environment. The bus is configured in such a way... |
| US-6,243,775 |
System for extending the available number of configuration registers A system for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent... |
| US-6,243,774 |
Apparatus program product and method of managing computer resources
supporting concurrent maintenance operations An apparatus, program product and method of managing computer resources each facilitate concurrent maintenance operations by automatically re-associating... |
| US-6,243,773 |
Configuration management system for hot adding and hot replacing devices A configuration management system and method for adding or replacing devices in a bus in a computer system. The configuration system creates and maintains a... |
| US-6,243,772 |
Method and system for coupling a personal computer with an appliance unit
via a wireless communication link to... The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first... |
| US-6,243,771 |
System for operating a communication channel in a mixed master/slave
subscriber environmental through a... A communication channel is operated in a mixed master/slave subscriber environment by a dynamical closing/opening operation. In particular, a separate... |
| US-6,243,770 |
Method for determining status of multiple interlocking FIFO buffer
structures based on the position of at least... One embodiment of the present invention relates to a method for using at least two first-in, first-out ("FIFO") buffers in a pipelined bus, comprising,... |
| US-6,243,769 |
Dynamic buffer allocation for a computer system A method for dynamically allocating buffers between components in a computer system is described. Matched sets of bidirectional buffers are used to control data... |
| US-6,243,768 |
Method and apparatus for controlling data transfer between a synchronous
DRAM-type memory and a system bus A method and an apparatus for a synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM... |
| US-6,243,767 |
System for register partitioning in multi-tasking host adapters by
assigning a register set and a unique... An integrated circuit includes a sequencer module that executes firmware command lines and a plurality of hardware I/O bus interface modules. The plurality of... |
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