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| Patent # | Description |
|---|---|
| US-6,243,866 |
Method and device for video, sound and data transmission Through a memory device and a control circuit on the transmitter side, temporal gaps are inserted into the data stream, said temporal gaps being removed again on... |
| US-6,243,865 |
Method of relaying digital video & audio data via a communication media A method of relaying digital video data over a communications medium such as the Internet is provided where accelerated relaying time can be realised. The method... |
| US-6,243,864 |
Compiler for optimizing memory instruction sequences by marking
instructions not having multiple memory address... Internal variables generated by a compiler are assigned to machine resources such as registers and memory by the resource assigning unit 11, and when the... |
| US-6,243,863 |
Apparatus and method for parallelizing legacy computer code A computer-implemented method and apparatus for parallelizing input computer-program code based on class-specific abstractions. The method includes the steps of... |
| US-6,243,862 |
Methods and apparatus for testing components of a distributed transaction
processing system A computer executable test language is provided for testing a component of a distributed transaction processing system implemented in accordance with the X/Open... |
| US-6,243,861 |
Object-oriented visual program development system for handling program
entity including pre-processing function... A program development system which develops a program sequence by generating a diagram composed of a combination of icons, and which can apply an object-oriented... |
| US-6,243,860 |
Mechanism employing a memory area for exchanging information between a
parent process and a child process... A computer system includes a central processing unit, a parent process for execution by the CPU, a child process for execution by the CPU, a memory accessible by... |
| US-6,243,859 |
Method of edit program codes by in time extracting and storing A method of extracting and saving program codes in time while the program is being edited. The program codes are analyzed and extracted according to a set of... |
| US-6,243,858 |
Program construction assisting system In a business application program construction system, various basic processing modules constituting a business application program have been prepared... |
| US-6,243,857 |
Windows-based flowcharting and code generation system A machine control system (130) includes a computer (132) that generates, edits and displays a continuous multi-block flowchart representing a program and... |
| US-6,243,856 |
System and method for encoding a scene graph A system and method for efficiently coding an animation sequence, converts a series of opcodes and associated opcode parameters into an array of integers. The... |
| US-6,243,855 |
Mask data design method A correction target segment extracted from the design pattern is divided into lengths suited for correction. If the arrangement of the divided segments is a... |
| US-6,243,854 |
Method for selecting hierarchical interactions in a hierarchical shapes
processor The method for selecting hierarchical interaction in a hierarchical shapes processor increases the operator's access and control over the handling of the... |
| US-6,243,853 |
Development of automated digital libraries for in-circuit testing of
printed curcuit boards An apparatus and method for developing digital libraries that are used in creating executable tests for testing devices at the board level. The present invention... |
| US-6,243,852 |
Method of and an apparatus for logic circuit synthesis For enabling to easily and efficiently perform analysis, logical checks and revisions of a logic circuit synthesized with automatic logic circuit synthesis, an... |
| US-6,243,851 |
Heterogeneous method for determining module placement in FPGAs The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further... |
| US-6,243,850 |
Allocation apparatus and method for determining cell allocation of
semiconductor circuit Not only a cell included in a semiconductor circuit but also a wiring net between cells is regarded as one node and thereby a network model is created. Then, the... |
| US-6,243,849 |
Method and apparatus for netlist filtering and cell placement Integrated circuit chip (IC) design and fabrication is a complex process requiring many stages including elaborate cell placement processes. The present... |
| US-6,243,848 |
Process for analyzing complex structures and system for implementing a
process of this type In order to ensure the conformance of a structure to its original specification, to regenerate a structure in accordance with technological developments, or to... |
| US-6,243,847 |
Parity insertion with precoder feedback in a PRML read channel A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a... |
| US-6,243,846 |
Forward error correction system for packet based data and real time media,
using cross-wise parity calculation A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio,... |
| US-6,243,845 |
Code error correcting and detecting apparatus An error correcting and detecting apparatus for a CD-ROM or DVD system executes a high speed decode process. The apparatus includes an input interface, a... |
| US-6,243,844 |
Signal transmitter used in the transmission of data in a communication
system A signal used in the transmission of data in a communication system including immediately successive cells for the purpose of cell synchronization, includes... |
| US-6,243,843 |
Post-mission test method for checking the integrity of a boundary scan test The invention is a method for assuring the integrity of a mission test. The method includes the steps of checking the integrity of the test after test execution... |
| US-6,243,842 |
Method and apparatus for operating on a memory unit via a JTAG port A method of controlling the operations of an on-chip memory unit includes the steps of receiving an indication of at least the ready or busy state of the memory... |
| US-6,243,841 |
Automated test and evaluation sampling system and method An automated test and evaluation sampling system includes a fast pattern memory (130) and a slow pattern memory (137) storing first and second sets of tests... |
| US-6,243,840 |
Self-test ram using external synchronous clock A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing... |
| US-6,243,839 |
Non-volatile memory system including apparatus for testing memory elements
by writing and verifying data patterns A memory system which includes apparatus for efficiently performing parallel testing of the integrity of the memory cells contained in multiple memory devices.... |
| US-6,243,838 |
Method for automatically reporting a system failure in a server A method of reporting a system failure in a server system, which includes the following acts: detecting a system failure condition; transmitting failure... |
| US-6,243,837 |
Microcomputer with the capability of suppressing signals which reset a
watchdog-timer A microcomputer (10) is proposed, which includes a central processing unit (11), a non-volatile memory (13), a volatile memory (14), a monitoring circuit (12)... |
| US-6,243,836 |
Apparatus and method for circular buffering on an on-chip discontinuity
trace The present invention is embodied in a method and apparatus for generating a complete discontinuity trace of instruction execution by a digital processor... |
| US-6,243,835 |
Test specification generation system and storage medium storing a test
specification generation program A test specification generation system which utilizes a repository of design information entered in a design process so as to enhance operational efficiency of a... |
| US-6,243,834 |
Apparatus and method for capturing information off a plurality of
bi-directional communications buses An apparatus for capturing data transmitted over of a plurality of bi-directional communication buses is provided. The apparatus comprises a plurality of trace... |
| US-6,243,833 |
Apparatus and method for self generating error simulation test data from
production code A method and apparatus for automatically testing device drivers is disclosed. The invention is applicable to any system wherein software or a device driver... |
| US-6,243,832 |
Network access server testing system and methodology A network access test system includes a test computer system having a modem bank coupled to a network access server via a telephone switch. The network access... |
| US-6,243,831 |
Computer system with power loss protection mechanism A computer system protects against loss of a computer's volatile data using system ROM and operating system resources. Upon entry into a reduced power state, or... |
| US-6,243,830 |
State information managing method and communication system In a communication system wherein a collecting communication unit of a plurality of communication units collects state information from report communication... |
| US-6,243,829 |
Memory controller supporting redundant synchronous memories A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units... |
| US-6,243,828 |
System for parallel, remote administration of mirrored and alternate volume
groups in a distributed data... A system for remotely administering one or more nodes of a distributed data processing system to provide mirroring of operating system images, and/or designating... |
| US-6,243,827 |
Multiple-channel failure detection in raid systems This invention is a software-based method for facilitating the recovery of a RAID storage system from the simultaneous failure of two or more disks (catastrophic... |
| US-6,243,826 |
Redundant network management system for a stakable fast ethernet repeater Provided is a redundant network management system. Several network management modules (NMMs), preferably one for each repeater unit, are provided in a single... |
| US-6,243,825 |
Method and system for transparently failing over a computer name in a
server cluster A method and system for transparently failing over a computer name with a legacy application running in a server cluster. When the application is set for failing... |
| US-6,243,824 |
Array disk subsystem An array disk subsystem including a command selector for separating a signal from a host into a data item and a command, a data dividing unit for subdividing the... |
| US-6,243,823 |
Method and system for boot-time deconfiguration of a memory in a processing
system A method and system for deconfiguring software in a processing system is disclosed. In one aspect, a processing system comprises a central processing unit (CPU),... |
| US-6,243,822 |
Method and system for asynchronous array loading The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array... |
| US-6,243,821 |
System and method for managing power consumption in a computer system Waking a computer from a system state. A wake data structure enables a device to wake the computer from a sleeping state. The lowest system state is identified... |
| US-6,243,820 |
Process and apparatus for reducing power usage in microprocessor devices
according to the type of activity... A process and apparatus for preparing the process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator... |
| US-6,243,819 |
Lid switch in portable computers and the power management system using the
same A portable computer supported by a power management system that responds to a closed state and an open state of a flat panel display. A closed position and an... |
| US-6,243,818 |
Power subsystem for a communication network containing a power bus A method and apparatus of powering components on a network by using a load-share technique and by using over-voltage and current-limiting circuitry. The power... |
| US-6,243,817 |
Device and method for dynamically reducing power consumption within input
buffers of a bus interface unit A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of... |
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