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| Patent # | Description |
|---|---|
| US-6,310,827 |
Electronic memory and electronic device provided with such a memory The electronic memory (2) includes blocks (M1 to MN) associated respectively with protective sequences (P1 to PN) and decision units (D1 to DN) which control... |
| US-6,310,826 |
Semiconductor device having a test circuit A semiconductor memory device includes a memory circuit from which data is read in correspondence with a first reference clock signal. A multiplexer outputs the... |
| US-6,310,825 |
Data writing method for semiconductor memory device A semiconductor memory device includes a control circuit that sets read and write latency periods such that the write data input circuit is activated and... |
| US-6,310,824 |
Integrated memory with two burst operation types The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an... |
| US-6,310,823 |
Circuit for generating internal column strobe signal in synchronous
semiconductor memory device A synchronous semiconductor memory device, comprising: burst signal generation means for generating a burst signal for controlling generation of an internal... |
| US-6,310,822 |
Delay locking high speed clock synchronization method and circuit A clock synchronizer circuit provides an internal clock signal for an integrated circuit that is synchronized to an external system clock signal, such that the... |
| US-6,310,821 |
Clock-synchronous semiconductor memory device and access method thereof A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a... |
| US-6,310,820 |
Relaxed write timing for a memory device A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous... |
| US-6,310,819 |
Method and apparatus for controlling the operation of an integrated circuit
responsive to out-of-synchronism... A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto... |
| US-6,310,818 |
Semiconductor memory device and method of changing output data of the same The present invention provides a method for changing output data of a multiple-port semiconductor memory device, including memory cells, first and second bit... |
| US-6,310,817 |
Multi-bank memory with word-line banking, bit-line banking and I/O
multiplexing utilizing tilable interconnects A multiple bank memory array includes a combined memory array, an X-decoder, a first word-line driver, a second word-line driver, a reference column, a... |
| US-6,310,816 |
Method and system for accessing rows in multiple memory banks within an
integrated circuit A row command unit is contained in an integrated circuit including a plurality of memory banks. The row command unit includes a plurality of row control latches,... |
| US-6,310,815 |
Multi-bank semiconductor memory device suitable for integration with logic Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these... |
| US-6,310,814 |
Rambus DRAM (RDRAM) apparatus and method for performing refresh operations An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a... |
| US-6,310,813 |
Methods and apparatus for bypassing refreshing of selected portions of DRAM
devices Refreshing of a portion of a DRAM device is bypassed when carrying out a refreshing operation on the DRAM device. By bypassing the refreshing of a portion of the... |
| US-6,310,812 |
Integrated memory having memory cells and reference cells Memory cells are arranged at crossover points of word lines WLi and bit lines. First reference cells are arranged at crossover points of at least one first... |
| US-6,310,811 |
Memory with high speed reading operation using a switchable reference
matrix ensuring charging speed A semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section... |
| US-6,310,810 |
High-speed sense amplifier The invention pertains to a high-speed sense amplifier and to a method to operate the sense amplifier. The sense amplifier to which a power supply voltage can be... |
| US-6,310,809 |
Adjustable pre-charge in a memory A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit... |
| US-6,310,808 |
Semiconductor memory device having structure for high-speed data processing The semiconductor memory device separates data input/output lines into a pair of write data lines and a pair of read data lines. A write gate is turned on with a... |
| US-6,310,807 |
Semiconductor integrated circuit device including tester circuit for
defective memory cell replacement Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value... |
| US-6,310,806 |
Semiconductor memory device with redundant circuit A redundant memory circuit stores a defective row address. A switch circuit connects a spare row decoder with the wire for transmitting a row address signal... |
| US-6,310,805 |
Architecture for a dual-bank page mode memory with redundancy A memory circuit (100) includes address circuitry (104) configured to receive address data and a plurality of I/O buffers (112). A core cell array (102) includes... |
| US-6,310,804 |
Device and method for repairing a semiconductor memory A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders... |
| US-6,310,803 |
Semiconductor having mechanism capable of operating at high speed A semiconductor memory device allowing low power consumption and a high speed operation is provided. The semiconductor memory device includes a spare replacement... |
| US-6,310,802 |
Method and apparatus for reducing bleed currents within a DRAM array having
row-to-column shorts A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously... |
| US-6,310,801 |
Method and device for fast addressing redundant columns in a nonvolatile
memory A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns,... |
| US-6,310,800 |
Non-volatile semiconductor memory device and method for driving the same A non-volatile semiconductor memory device of the present invention includes, on a semiconductor substrate, a plurality of memory cells arranged in a matrix, a... |
| US-6,310,799 |
Negative resistance device A negative resistance device (NRD) has a MOSFET-like structure, and is biased by shorting the gate and source together at a fixed applied potential and applying... |
| US-6,310,798 |
Semiconductor memory and method for manufacture thereof A semiconductor memory which can secure the stability of data holding characteristics and data read/write characteristics for a tunnel diode having a small... |
| US-6,310,797 |
Drive method for FeRAM memory cell and drive device for the memory cell A method is disclosed for driving a memory cell formed of a ferroelectric capacitor FC and a transistor Tr. While maintaining a cell plate line CP at an... |
| US-6,310,796 |
Dynamic random access memory device and .mu.BGA package using multiple
reference voltage pads A dynamic random access memory device and a .mu.BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n... |
| US-6,310,795 |
Semiconductor memory device with data retention characteristic of improved
stability During standby, bit lines BL1 and /BL1 are precharged, and the potentials of word lines WL1 and WL2 are set at a potential slightly higher than a ground... |
| US-6,310,794 |
Upgradable storage system The present disclosure relates to an upgradable storage system. The storage system comprises a memory device compartment that is adapted to receive memory... |
| US-6,310,793 |
Segmented word line architecture for dividing up a word line into a
plurality of banks for cell arrays having... The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately... |
| US-6,310,792 |
Shared package for VRM and processor unit A component module includes a processor and at least a portion of a voltage regulator module which regulates voltages being supplied to said processor. |
| US-6,310,791 |
Power rectifier A power rectifier includes a heat dissipation base, a hollow hexagonal gasket soldered to the heat dissipation base around a flat, circular projection of the... |
| US-6,310,790 |
High frequency DC-DC down converter with power feedback for improved power
factor In a downconverter for supplying a DC current to a lamp, power feedback is achieved by adding a high frequency-operated switch and a capacitor to the topology.... |
| US-6,310,789 |
Dynamically-controlled, intrinsically regulated charge pump power converter A charge pump power converter efficiently provides electrical power by dynamically controlling a switch matrix of the charge pump. Instead of open-loop... |
| US-6,310,788 |
Three-way, three phase power divider and combiner The invention relates to a three-way, three-phase power divider or combiner. More specifically, the invention will split or combine power into three different... |
| US-6,310,787 |
Multiway power converter A switching power converter capable of operation in either Nonconversion, Stepdown, or Stepup Mode. Included is a parallel circuit of three serial connections of... |
| US-6,310,786 |
Switching power-supply circuit The present invention relates to a switching power-supply circuit comprising: rectifying and smoothing means for generating a rectified and smoothed voltage and... |
| US-6,310,785 |
Zero voltage switching DC-DC converter A DC-DC power converter includes input terminals and a rectifier circuit. An additional circuit is connected to the input terminals and the rectifier. The latter... |
| US-6,310,784 |
Densely arranged electrically shielded communication panels Apparatus and method for supporting a large number of densely arranged and electrically shielded panels are disclosed. To achieve shielding each panel has a... |
| US-6,310,783 |
Modular method and apparatus for building an uninterruptible power system
(UPS) An electrical cabinet or chassis for an uninterruptible power system (UPS system) includes universal bays or slots that can receive either power modules or... |
| US-6,310,782 |
Apparatus for maximizing memory density within existing computer system
form factors A system includes a memory module formed of a first portion having a first side that directly connects to a mount in the system, which first side is of a first... |
| US-6,310,781 |
Connection pin layout for connecting integrated magnetics modules to a
printed circuit board A connection pin layout for connecting one or more integrated magnetics modules (IMMs) to a printed circuit board (PCB) for reduced electromagnetic interference... |
| US-6,310,780 |
Surface mount assembly for electronic components A plurality of indentations 21, 22, and 23 are formed in one major surface of a printed board 1. A plurality of electrode pads 41, 42, 43, and 44 are provided on... |
| US-6,310,779 |
System for attaching cartridge-type CPU to a board The system provided attaches a cartridge-type central processor unit (CPU) to a motherboard and includes a first device, a second device and a third device. The... |
| US-6,310,778 |
IC board module for producing an IC board and process for producing an IC
board An IC card module (20) for producing an IC card (118) having at least one coil (46) and at least one chip (23) for the formation of a transponder unit, with the... |
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