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| Patent # | Description |
|---|---|
| US-6,381,194 |
OUTPUT CIRCUIT FOR A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, DOUBLE
DATA RATE DYNAMIC RANDOM ACCESS... A method and apparatus for synchronizing output data and data strobe signals uses internal interleaved clock signals in a double data rate (DDR) DRAM that are... |
| US-6,381,193 |
Apparatus for externally timing high voltage cycles of non-volatile memory
system An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be... |
| US-6,381,192 |
Address buffer in a flash memory An address buffer in a flash memory includes a buffer section for buffering external addresses to select specific sectors in the flash memory, a code storage... |
| US-6,381,191 |
Fast accessible dynamic type semiconductor memory device Respective ones of a plurality of memory array blocks are rendered drivable independently of each other under control of an array activation control circuit.... |
| US-6,381,190 |
Semiconductor memory device in which use of cache can be selected A semiconductor memory device, includes a plurality of banks, each of which includes a memory cell array and a sense amplifier section, a plurality of channel... |
| US-6,381,189 |
Semiconductor register element To provide a semiconductor register element being capable of reducing standby power consumption of a CMOS semiconductor integrated circuit. Upon shifting from a... |
| US-6,381,188 |
DRAM capable of selectively performing self-refresh operation for memory
bank A dynamic random access memory (DRAM) including a plurality of memory banks is capable of selectively performing a self-refresh operation with respect to only a... |
| US-6,381,187 |
Sense amplifier circuit for use in a semiconductor memory device Disclosed herein is a sense amplifier circuit which includes a first, a second and a third similar load transistors. The first and second load transistors supply... |
| US-6,381,186 |
Dynamic random access memory A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same... |
| US-6,381,185 |
Method and a circuit architecture for testing an integrated circuit
comprising a programmable, non-volatile memory A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The... |
| US-6,381,184 |
Method and apparatus for rapidly testing memory devices A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of... |
| US-6,381,183 |
Column redundancy for prefetch An integrated memory circuit is provided having at least one subtractor coupled to each redundant fuse set for subtracting a predetermined value from a known... |
| US-6,381,182 |
Combined tracking of WLL and VPP low threshold voltage in DRAM array In generating first and second voltages (VPP and WLL) for respectively activating and deactivating transistors of a DRAM array that transfer charge to cells of... |
| US-6,381,181 |
Timing independent current comparison and self-latching data circuit The self-latching data circuit reads data from a pair of memory cells and latches the read data in response to a single transition of an enable signal. The... |
| US-6,381,180 |
Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a... |
| US-6,381,179 |
Using a negative gate erase to increase the cycling endurance of a
non-volatile memory cell with an... An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve... |
| US-6,381,178 |
Non-volatile semiconductor memory device and method of rewriting data
stored in non-volatile semiconductor... There is provided a non-volatile semiconductor memory device, including (a) a first gate insulating film formed on a channel region of a semiconductor substrate,... |
| US-6,381,177 |
Method for controlled soft programming of non-volatile memory cells, in
particular of the flash EEPROM and... A method for controlled soft programming of a plurality of non-volatile memory cells, having bulk terminals connected to one another and to a common bulk line.... |
| US-6,381,176 |
Method of driving remapping in flash memory and flash memory architecture
suitable therefor A method of driving remapping in a flash memory, which is capable of writing the status of a block and a unit by reducing the number of partial write cycles as... |
| US-6,381,175 |
Method and system for validating flash memory A method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory... |
| US-6,381,174 |
Non-volatile memory device with redundant columns A non-volatile memory device includes an array of erasable blocks of non-volatile memory cells. At least one of the blocks has at least one redundant column. A... |
| US-6,381,173 |
Serial-flash, EPROM, EEPROM and flash EEPROM nonvolatile memory in AMG
configuration A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a... |
| US-6,381,172 |
Memory apparatus including programmable non-volatile multi-bit memory cell,
and apparatus and method for... Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The... |
| US-6,381,171 |
Magnetic element, magnetic read head, magnetic storage device, magnetic
memory device The present invention provides a spin-dependent tunneling effect element expectable to offer the spin accumulation effect at room temperature while also... |
| US-6,381,170 |
Ultra high density, non-volatile ferromagnetic random access memory A random access memory element utilizes giant magnetoresistance. The element includes at least one pair of ferromagnetic layers sandwiching a nonmagnetic... |
| US-6,381,169 |
High density non-volatile memory device This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory... |
| US-6,381,168 |
Circuits and methods for a memory cell with a trench plate trench capacitor
and a vertical bipolar read device A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction... |
| US-6,381,167 |
Semiconductor memory device including plurality of global data lines in
parallel arrangement with low parasitic... A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data... |
| US-6,381,166 |
Semiconductor memory device having variable pitch array A memory cell array (300) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines (302a) having a first pitch, and... |
| US-6,381,165 |
Semiconductor memory device having storage node electrodes offset from each
other A semiconductor memory device that is capable of reducing the probability of a bridge being generated between storage node electrodes, and a mask pattern for... |
| US-6,381,164 |
Low profile, high density memory system The present invention provides a low profile, high density electronic package for high speed, high performance semiconductors, such as memory devices. It... |
| US-6,381,163 |
Methods and apparatus for reading a CAM cell using boosted and regulated
gate voltage A memory device with a CAM cell and a read circuit are disclosed for reading a CAM cell using a boosted CAM gate voltage. The CAM read circuit comprises a... |
| US-6,381,162 |
Circuitry and method for controlling current surge on rails of
parallel-pulldown-match-detect-type content... A content addressable memory system has an array of CAM cells. Each row of the array has a match line coupled to a match line pull device. The match line pull... |
| US-6,381,161 |
Low-inductance circuit arrangement The invention relates to a circuit with low parasitic inductances, reduced current flow paths, and reduced current-circumfusion. The circuit includes a ceramic... |
| US-6,381,160 |
Converter comprising resonant circuit elements The invention relates to a converter comprising switching elements for chopping a direct voltage, in which turn-on phases of the switching elements alternate... |
| US-6,381,159 |
Inductor current synthesizer for switching power supplies A circuit and method for sensing the inductor current flowing to a load from a switching power supply without using a sense resistor in the path of the inductor... |
| US-6,381,158 |
System and method for monitoring DC link capacitance in three level
inverters A signal is injected into a neutral point regulator of an inverter drive. The response to that injected signal is monitored as an indication of the capacitance... |
| US-6,381,157 |
Independent load sharing between parallel inverter units in an AC power
system For independent load sharing of current harmonics between parallel inverter units (1a, 1b, 1c) in an AC power system without intra-unit control signal ... |
| US-6,381,156 |
Uninterruptible duplexed power supply system, and unit plug-in structure
for uninterruptible duplexed power... It is an object of the present invention to provide an uninterruptible duplexed power supply system that is highly reliable and has excellent durability, with... |
| US-6,381,155 |
Method for clusterized power sharing conversion and regulation of the
primary power source within a converting... A method for clusterized power sharing conversion and regulation of the primary source power within the power converting and regulating supplies includes... |
| US-6,381,154 |
PWM nonlinear controller with a single cycle response and a non resettable
integrator A single-cycle response pulse width modulator comprising a single error integrating amplifier. The error integrator output is compared to zero to set a... |
| US-6,381,153 |
Method and apparatus of EMI filtering that eliminates the need for an
inductor An EMI filter for use with a motor driven blower connectable to an inflatable portion of a patient support powered by two supply lines includes a blower ground... |
| US-6,381,152 |
Method of driving semiconductor switching device in non-saturated state and
power supply apparatus containing... A power supply apparatus includes a semiconductor switching device for outputting power and a control circuit for controlling the on/off operation of the... |
| US-6,381,151 |
High efficiency switching controller A high efficiency switching controller for use in a switching power supply (SPS) includes a current control device coupled to a voltage source of the SPS and a... |
| US-6,381,150 |
Isolated dual converter having primary side internal feedback for output
regulation The present invention comprises an isolated dual power supply having an internal feedback loop. The dual power supply comprises a modulated switched power... |
| US-6,381,149 |
Cardguide retainer A printed circuit board retainer. The printed circuit board retainer directs the movement of a printed circuit board during installation into an enclosure. In a... |
| US-6,381,148 |
Dual processor retention assembly A processor retention assembly is disclosed. An embodiment of the processor retention assembly includes a first dual processor retention module and a second dual... |
| US-6,381,147 |
Card guide including air deflector means A card guide which optimizes the flow of forced cooling air, provides for self alignment to a host motherboard and provides for integrated ESD hazard mitigation,... |
| US-6,381,146 |
Module removal system The invention includes a latch assembly movably mounted on a module. The module is removably supportably on a chassis, and movement of the latch assembly with... |
| US-6,381,145 |
Computer enclosure incorporating a catch A computer enclosure includes a chassis (60) and a hood (10) attached to the chassis. The chassis includes a rear panel (90) defining a slot (91) and a pair of... |
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