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| Patent # | Description |
|---|---|
| US-6,381,698 |
System and method for providing assurance to a host that a piece of
software possesses a particular property A system and method for providing assurance to a host executing a piece of software that the software possesses a particular property. A certifier determines if... |
| US-6,381,697 |
Electronic equipment, method of controlling operation thereof and
controlling method A method and apparatus for controlling communication between components connected to a bus. All equipment manufacturers may use every application available on... |
| US-6,381,696 |
Method and system for transient key digital time stamps Irrefutable public key digital signature time-stamps are created and used based upon, for example, the concept of transient time-interval-related secret... |
| US-6,381,695 |
Encryption system with time-dependent decryption An object of the invention is to provide an encryption system and method for inhibiting the decryption of encrypted data unless a decryption condition is... |
| US-6,381,694 |
System for automatic recovery from software problems that cause computer
failure A system for recovering from certain types of system software startup problems employs a user-hidden secondary startup volume stored in the computer. During a... |
| US-6,381,693 |
Arrangements having firmware support for different processor types A system, a method of operating the system and a system firmware. The system includes a processor and a system firmware including a plurality of customized... |
| US-6,381,692 |
Pipelined asynchronous processing An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A... |
| US-6,381,691 |
Method and apparatus for reordering memory operations along multiple
execution paths in a processor A method is provided for scheduling instructions for execution along multiple paths in a Computer processing system implementing out-of-order execution. The... |
| US-6,381,690 |
Processor for performing subword permutations and combinations An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without... |
| US-6,381,689 |
Line-oriented reorder buffer configured to selectively store a memory
operation result in one of the plurality... A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a... |
| US-6,381,688 |
Serial port for a hose adapter integrated circuit using a single terminal A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial... |
| US-6,381,687 |
Flexible memory channel A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means... |
| US-6,381,686 |
Parallel processor comprising multiple sub-banks to which access requests
are bypassed from a request queue... A parallel processor capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks from... |
| US-6,381,685 |
Dynamic configuration of memory module using presence detect data A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic... |
| US-6,381,684 |
Quad data rate RAM A quad data rate RAM (100) in accordance with the invention is a burst synchronous RAM with separate data buses (Data-In, Data-Out) for read and write data. Data... |
| US-6,381,683 |
Method and system for destination-sensitive memory control and access in
data processing systems A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request... |
| US-6,381,682 |
Method and apparatus for dynamically sharing memory in a multiprocessor
system Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected... |
| US-6,381,681 |
System and method for shared memory protection in a multiprocessor computer A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer (10) having a plurality of... |
| US-6,381,680 |
Data processing system with an enhanced cache memory control A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request... |
| US-6,381,679 |
Information processing system with prefetch instructions having indicator
bits specifying cache levels for... An information processing unit and method for controlling a cache according to a software prefetch instruction, are disclosed. Indication bits are provided for... |
| US-6,381,678 |
Processing ordered data requests to a memory A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The... |
| US-6,381,677 |
Method and system for staging data into cache Disclosed is a system for caching data. After determining a sequential access of a first memory area, such as a direct access storage device (DASD), a processing... |
| US-6,381,676 |
Cache management for a multi-threaded processor A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among... |
| US-6,381,675 |
Switching mechanism and disk array apparatus having the switching mechanism The present invention enables to obtain a data transfer at a high rate, at a reasonable cost, and with a high reliability. The disk array system according to the... |
| US-6,381,674 |
Method and apparatus for providing centralized intelligent cache between
multiple data controlling elements Apparatus and methods which allow multiple storage controllers sharing access to common data storage devices in a data storage subsystem to access a centralized... |
| US-6,381,673 |
Method and apparatus for performing a read next highest priority match
instruction in a content addressable... A content address memory (CAM) device that implements a read next highest priority or "RNHPM" instruction. The CAM device initially searches its CAM locations... |
| US-6,381,672 |
Speculative opening of a new page when approaching page boundary during
read/write of isochronous streams A memory controller detects an approaching end of a currently open page for an access operation for a particular data stream. The memory controller, in response... |
| US-6,381,671 |
Semiconductor integrated circuit and data processing system To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are... |
| US-6,381,670 |
Flash memory array having maximum and minimum threshold voltage detection
for eliminating over-erasure problem... A flash memory having over-erased cells eliminated and comprising adjustable erase and program conditions. The maximum and minimum threshold voltages of the... |
| US-6,381,669 |
Multi-bank, fault-tolerant, high-performance memory addressing system and
method A memory addressing system for a multi-bank memory device that generally provides no bank conflicts for stride 1 data access patterns and infrequent ban... |
| US-6,381,668 |
Address mapping for system memory For optimizing access to system memory having a plurality of memory banks, interleaving can be used when storing data so that data sequences are distributed over... |
| US-6,381,667 |
Method for supporting multiple delayed read transactions between computer
buses One embodiment of the present invention provides a method that supports multiple delayed read transactions between a host bus and a peripheral bus in a computer... |
| US-6,381,666 |
Method and apparatus for extending the range of the universal serial bus
protocol The present invention provides a method and apparatus to be used to extend the range of a standard USB devices. An extended range hub is provided which comprises... |
| US-6,381,665 |
Mechanisms for converting interrupt request signals on address and data
lines to interrupt message signals In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data... |
| US-6,381,664 |
System for multisized bus coupling in a packet-switched computer system A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus... |
| US-6,381,663 |
Mechanism for implementing bus locking with a mixed architecture An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to... |
| US-6,381,662 |
Removable mother/daughter peripheral card A peripheral card having a Personal Computer ("PC") card form factor and removably coupled externally to a host system is further partitioned into a mother card... |
| US-6,381,661 |
High throughput UART to DSP interface having Dual transmit and receive FIFO
buffers to support data transfer... The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are... |
| US-6,381,660 |
Clock generating system generating clock based on value obtained by adding
second time information and... An input device sequentially receives a first packet and a second packet that immediately follows the first packet, each of the first and second packets... |
| US-6,381,659 |
Method and circuit for controlling a first-in-first-out (FIFO) buffer using
a bank of FIFO address registers... A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between... |
| US-6,381,658 |
Apparatus and method to precisely position packets for a queue based memory
controller Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue... |
| US-6,381,657 |
Sharing list for multi-node DMA write operations In a SCI based multi-node system, the write purge command joins the new node that is requesting to write to the memory of the sharing list, while maintaining the... |
| US-6,381,656 |
Method and apparatus for monitoring input/output ("I/O") performance in I/O
processors A method and system for monitoring performance of an input/output ("I/O") processor in a server associated with a computing system, such as an intelligent I/O... |
| US-6,381,655 |
System for transmitting information about an electronic unit stored in a
storage means having a hierarchical... A method for transmitting information between each electronic unit, comprising the steps of (a) transmitting information whose amount does not exceed a... |
| US-6,381,654 |
Systems methods and computer program products for customized host access
applications including... Host communications software is modified to include user-provided transport code for sending and receiving datastreams to and from a host. A user transport code... |
| US-6,381,653 |
Managing accidental death of an object during communication between objects
distributed in a COM environment A method in a COM environment enables a first object (X) to be informed of an accidental death of one or more second objects (Y). When the first object (X) opens... |
| US-6,381,652 |
High bandwidth processing and communication node architectures for
processing real-time control messages An architecture for processing time-critical real-time control messages in a large real-time processing system. Control messages are separated from block data... |
| US-6,381,651 |
Information processing apparatus and method enabling users to easily
acquire information that occurs on a... A server computer stores user favorites information that relates to the favorites of a user. Whether digital information that has newly occurred on a network... |
| US-6,381,650 |
Method for finding the address of a workstation assigned a dynamic address A protocol for locating a server program on a workstation that is dynamically allocated IP address is disclosed. To located a desired server program, a special... |
| US-6,381,649 |
Data flow monitoring at a network node using periodically incremented
counters for comparison to predetermined... An apparatus and method for monitoring data flow at a node on a network are disclosed. A memory location or "bucket" is allocated to each of a plurality of links... |
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