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| Patent # | Description |
|---|---|
| US-6,380,792 |
Semiconductor integrated circuit A semiconductor integrated circuit capable of achieving drain current and transconductance required for driving an analog switch even after lowering a supply... |
| US-6,380,791 |
Circuit including segmented switch array for capacitive loading reduction An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies... |
| US-6,380,790 |
Integrator topplogy for continuous integration An apparatus includes a switching circuit, an integrator circuit having an input for receiving a first signal from the switching circuit, a sensing circuit... |
| US-6,380,789 |
Switched input circuit structure A switched input circuit structure of the type which includes an input terminal receiving an input voltage and an output terminal connected to an input... |
| US-6,380,788 |
Programmable clock trunk architecture A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit... |
| US-6,380,787 |
Integrated circuit and method for minimizing clock skews An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver... |
| US-6,380,786 |
Digital phase lock loop A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output... |
| US-6,380,785 |
Method and apparatus for eliminating shoot-through events during
master-slave flip-flop scan operations A novel method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations to allow minimal test time of electronic circuit... |
| US-6,380,784 |
Circuit for generating sense amplifier control signal for semiconductor
memory A circuit is provided that generates a sense amplifier control signal for a semiconductor memory in which signal paths for a normal operation and a refresh... |
| US-6,380,783 |
Cyclic phase signal generation from a single clock source using current
phase interpolation A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of... |
| US-6,380,782 |
Integrated circuit The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to... |
| US-6,380,781 |
Soft error rate tolerant latch A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors... |
| US-6,380,780 |
Integrated circuit with scan flip-flop An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock,... |
| US-6,380,779 |
Edge-triggered, self-resetting pulse generator An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage... |
| US-6,380,778 |
Semiconductor integrated circuit Even if duty is shifted to either a state in which an "H" period is long or a state in which an "L" period is long, the duty is recovered to about 50%. A duty... |
| US-6,380,777 |
Output driver having controlled slew rate An off chip driver circuit is adapted to output differential output signals at high speed rate and capable to drive high external loads without degradation of... |
| US-6,380,776 |
Electrical signal synchronization Digital circuitry synchronizes clock signals in a digital circuit. A value of a reference clock is sampled at a plurality of points near a transition point of a... |
| US-6,380,775 |
Multiplexed distribution system for CMOS signals First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked... |
| US-6,380,774 |
Clock control circuit and clock control method A clock control circuit which includes a frequency multiplying interpolator for generating and outputting multiphase clocks by frequency multiplying an input... |
| US-6,380,773 |
Prescalar using fraction division theory A prescalar using the fractional division theory. The prescalar is a critical circuit in a phase-locked loop based frequency synthesizer to provide a high... |
| US-6,380,772 |
Self-limiting pad driver A complementary self-limiting transmission line driver is capable of driving an unterminated line driver with self-limiting slew rate control to minimize the... |
| US-6,380,771 |
Method of driving power circuit and circuit therefor A power drive circuit having push-pull type output transistors connected in series between power supplies. The power drive circuit comprises an idling loop for... |
| US-6,380,770 |
Low ground bounce and low power supply bounce output driver with dual,
interlocked, asymmetric delay lines Ground bounce and power supply bounce are reduced in an output driver by utilizing a plurality of p-channel and n-channel driver transistors which are connected... |
| US-6,380,769 |
Low voltage output drive circuit A trigger circuit (22) having a depletion mode n-type transistor (32) and a depletion mode p-type transistor (34) operate by having each gate thereof driven by... |
| US-6,380,768 |
Display device capable of collecting substantially all power charged to
capacitive load in display panel There is provided a display device composed of a display panel having a capacitive load such as an ELDP and a PDP and a semiconductor device for driving the... |
| US-6,380,767 |
Connection control circuit A connection control circuit is provided to guarantee a high quality of port-to-port connection service by enabling to maintain the suspended state even when a... |
| US-6,380,766 |
Integrated circuitry for use with transducer elements in an imaging system Integrated circuitry for use with an ultrasound transducer of an ultrasound imaging system is disclosed. According to one embodiment of the invention, unique... |
| US-6,380,765 |
Double pass transistor logic with vertical gate transistors Systems and methods are provided for double pass transistor logic with vertical gate transistors. The vertical gate transistors have multiple vertical gates... |
| US-6,380,764 |
Semiconductor integrated circuit device, recording medium stored with cell
library, and method for designing... Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a... |
| US-6,380,763 |
Charge switch control circuit A charge control circuit which prevents charging of a battery when a charger is connected to the battery when the voltage of the battery is not above a threshold... |
| US-6,380,762 |
Multi-level programmable voltage control and output buffer with selectable
operating voltage An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a... |
| US-6,380,761 |
Level converter provided with slew-rate controlling means A level converter for the converting of a first digital signal (U.sub.1) having a first voltage range into a second digital signal (U.sub.2) having a second... |
| US-6,380,760 |
Integrated circuit for handling buffer contention and method thereof In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The... |
| US-6,380,759 |
Variable grain architecture for FPGA integrated circuits A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB... |
| US-6,380,758 |
Impedance control for wide range loaded signals using distributed
methodology In one embodiment of the present invention, a compensation controller includes a counter, K driving circuits, K feedback circuits, and a state machine. The... |
| US-6,380,757 |
Start pulse rejection for a motor commutation pulse detection circuit Improved motor position detection circuitry based on commutation pulse counting, including a pulse recognition circuit, a pulse counting circuit, and a start... |
| US-6,380,756 |
Burin carrier and semiconductor die assembly A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention... |
| US-6,380,755 |
Testing apparatus for test piece testing method contactor and method of
manufacturing the same An apparatus of the present invention for testing a test piece comprises a contactor including a clock circuit capable of varying the frequency and a pattern... |
| US-6,380,754 |
Removable electrical interconnect apparatuses including an engagement
proble A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a)... |
| US-6,380,753 |
Screening method of semiconductor device and apparatus thereof A power supply applies a power supply voltage to a large number of devices formed on a wafer W. In the state where the devices are quiescent, the quiescent power... |
| US-6,380,752 |
IC socket A minute shielded loop probe is built in the vicinity of the terminal of the IC socket. The IC is fixed to the IC socket and driven by the external power source... |
| US-6,380,751 |
Wafer probe station having environment control enclosure A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such... |
| US-6,380,750 |
Capacitance probe and spacer therefor A capacitance probe including a spacer for separating an inner conductor from an outer conductor. The spacer has a member that substantially surrounds the outer... |
| US-6,380,749 |
Apparatus for measuring properties of a moving paper web or cardboard web The invention relates to an apparatus for measuring properties of a moving paper web or cardboard web. The apparatus comprises a sensor and a counterpart. The... |
| US-6,380,748 |
Apparatus and method for diagnosing antennas using switches An apparatus and method for diagnosing antennas using switches, wherein a system is configured in such a manner that a plurality of switches determine a data... |
| US-6,380,747 |
Methods for processing, optimization, calibration and display of measured
dielectrometry signals using property... A method is disclosed for processing, optimization, calibration, and display of measured dielectrometry signals. A property estimator is coupled by way of... |
| US-6,380,746 |
Monitoring fluid condition with a spiral electrode configuration A plug for insertion through the wall of a vessel filled with fluid to be monitored has an extension immersed in the fluid which has a pair of wire electrodes... |
| US-6,380,745 |
Electrical geophysical apparatus for determining the density of porous
materials and establishing geo-electric... The invention includes an apparatus for determining geo-electric data and the density of a porous material. A resistivity-measuring device applies an electrical... |
| US-6,380,744 |
Shielding apparatus for selective attenuation of an electromagnetic energy
field component A shield apparatus for use in conjunction with a well tool to selectively attenuate one or more electromagnetic energy field components as the components... |
| US-6,380,743 |
Flexible traceable push rod A traceable push rod having a predetermined length comprising an inner layer, an intermediate layer and an outer layer. The inner layer characterized as being... |
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