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| Patent # | Description |
|---|---|
| US-6,381,748 |
Apparatus and methods for network access using a set top box and television An Internet gateway video server transmits selection information to a set top box connected to a television. The set top box displays the selection information... |
| US-6,381,747 |
Method for controlling copy protection in digital video networks A method and system of providing copy protection of video analog and digital signals and the like, wherein the signals are transmitted via a digital delivery... |
| US-6,381,746 |
Scaleable video system having shared control circuits for sending multiple
video streams to respective sets of... A video system is comprised of: a) a single supervisor processor, and multiple co-processors which are selectable in number and are coupled via a bus to the... |
| US-6,381,745 |
Signal distribution system A system for distributing signals, in which a distribution module is coupled to each of a plurality of outlets by respective first and second cables. Each of the... |
| US-6,381,744 |
Automated survey kiosk An automated survey kiosk which is easy to install at a location, does not require access to standard telephone lines, can be easily reprogrammed, has unlimited... |
| US-6,381,743 |
Method and system for generating a hierarchial document type definition for
data interchange among software tools A method is disclosed for use in a software development framework having a repository and at least two software systems. The repository contains a meta-model and... |
| US-6,381,742 |
Software package management A software package manager uses a distribution unit containing components for a software package and a manifest file that describes the distribution unit to... |
| US-6,381,741 |
Secure data downloading, recovery and upgrading The invention provides an improved method and system for secure down-loading, recovery, and upgrading of data. A client device receives information from a server... |
| US-6,381,740 |
Method and system for incrementally improving a program layout A method and system for incrementally improving the layout of a program image of a computer program to reduce the working set. The system iteratively selects... |
| US-6,381,739 |
Method and apparatus for hierarchical restructuring of computer code A compiler (142) constructs (FIGS. 14-32) a Reduced Flowgraph (RFG) from computer source code (144). The RFG is used to instrument (FIG. 36) code (142). An... |
| US-6,381,738 |
Method for optimizing creation and destruction of objects in computer
programs Information is computed about the reachability relationships among objects and pointers to enable transformation of a computer program for optimizing the... |
| US-6,381,737 |
Automatic adapter/stub generator Systems and methods for automatically providing an adapter or a stub in a runtime environment are provided. An adapter generator is provided with input... |
| US-6,381,736 |
Method for compile-time type-checking of arguments for externally-specified
format strings A method for type-checking format arguments during compile time which uses data in an external file. Data from the external file is converted into a generated... |
| US-6,381,735 |
Dynamic classification of sections of software Dynamic classification of sections of software using a profile-based optimization system optimizes management of the sections of software. Software executes... |
| US-6,381,734 |
Method, software and apparatus for referencing a method in object-based
programming Method and apparatus for encapsulating a reference to a method in object-based programming systems and ensuring that the reference is safe are disclosed. The... |
| US-6,381,733 |
System and method for instantiating logic blocks within an FPGA A copying logic block for, and a method of, programming an FPGA and a modular music synthesis processor incorporating the copying logic block or the method. In... |
| US-6,381,732 |
FPGA customizable to accept selected macros A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the... |
| US-6,381,731 |
Placement based design cells injection into an integrated circuit design An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent... |
| US-6,381,730 |
Method and system for extraction of parasitic interconnect impedance
including inductance A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of... |
| US-6,381,729 |
Data processing system and method for efficient determination of return
current spread A data processing system and method are disclosed for efficiently determining a total return current spread at an evaluation point in a reference plane in a... |
| US-6,381,728 |
Partitioned interleaver memory for map decoder The present invention is a novel and improved technique for decoding with particular application to turbo, or iterative, coding techniques. In accordance with... |
| US-6,381,727 |
Apparatus and method for receiving data with bit insertion A receiver for data encoded as a series of symbols, each including a plurality of components such as the I and Q components of 16-QAM symbols or other... |
| US-6,381,726 |
Architecture for soft decision decoding of linear block error correcting
codes A method and apparatus for decoding a corrupted code word is described. Decoding is accomplished by using a decoder that has a common measure of reliability for... |
| US-6,381,725 |
Disk device and data error correction method thereof The storage unit of the present invention registers a plurality of data read conditions set in a plurality of parameters, an MPU reads data read conditions from... |
| US-6,381,724 |
Method and apparatus for modulation encoding data for storage on a
multi-level optical recording medium A system and method are disclosed for modulation encoding data for storage or transmission on a multilevel medium. The method includes encoding a first portion... |
| US-6,381,723 |
Error correction device for correcting error in input symbol string In an error correction device, a chain search operation unit supplies a symbol string which has undergone error correction to a first FILO unit and supplies a... |
| US-6,381,722 |
Method and apparatus for testing high speed input paths A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit... |
| US-6,381,721 |
Detecting communication errors across a chip boundary An integrated circuit provides for a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic,... |
| US-6,381,720 |
Test circuit and method for system logic There is disclosed a test circuit for testing a system logic constituted of an existing macro and a newly created circuit both mounted on a circuit board. A... |
| US-6,381,719 |
System and method for reducing clock skew sensitivity of a shift register The system and method of the present invention for reducing the clock skew sensitivity of a shift register provides a control circuit for generating a clock... |
| US-6,381,718 |
Current controlled multi-state parallel test for semiconductor device A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and... |
| US-6,381,717 |
Snoopy test access port architecture for electronic circuits including
embedded core having test access port... This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at... |
| US-6,381,716 |
System and method for testing devices sensitive to magnetic fields A high permeability magnetic core structure introduces a magnetic field to an intergrated circuit during testing. The magnetic core is mounted in an automatic... |
| US-6,381,715 |
System and method for performing parallel initialization and testing of
multiple memory banks and interfaces in... A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality... |
| US-6,381,714 |
Error detection method, error detection apparatus, and network system In a normal operation mode, paths in a communication IC are controlled so that data received from a transmission line and addressed to this node is captured into... |
| US-6,381,713 |
Method for responding to transmission errors in a digital communication
system according to characteristics of... In a digital communication system, a method is provided for recognizing and acting upon differences in information field characteristics when transmission errors... |
| US-6,381,712 |
Method and apparatus for providing an error messaging system A standard platform independent messaging environment for use with devices is provided. The environment provides programming and operational building blocks that... |
| US-6,381,711 |
Method and apparatus for unified, pre-addressed, context-sensitive
reporting A method, apparatus, and article of manufacture for reporting a context-sensitive comment to a pre-addressed destination is described. The method comprises the... |
| US-6,381,710 |
Error logging method utilizing temporary defect list An error logging method utilizes a temporary defect list to store errors produced at or above a predetermined occurrence frequency during a defect detecting... |
| US-6,381,709 |
Process and apparatus for downloading data from a server computer to a
client computer A download of a data file from a server computer to a client computer is monitored by the client computer. The download is restarted automatically if a failure... |
| US-6,381,708 |
Method for decoding addresses for a defective memory array The use of a partially defective memory array to create a non-defective memory array. In a manner transparent to the memory controller, an address decoder is... |
| US-6,381,707 |
System for decoding addresses for a defective memory array The use of a partially defective memory array to create a non-defective memory array. In a manner transparent to the memory controller, an address decoder is... |
| US-6,381,706 |
Fine granularity rewrite method and apparatus for data storage device A method for rewriting track packets that fail a check-after-write test onto a track of a storage medium is presented. Local packet address information is... |
| US-6,381,705 |
Method and device for reducing current consumption of a microcontroller A method and device reduces consumption of a microcontroller, allowing the microcontroller to enter into an "active halt" mode in which the central processing... |
| US-6,381,704 |
Method and apparatus for altering timing relationships of non-overlapping
clock signals in a microprocessor A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a... |
| US-6,381,703 |
Guaranteeing clock slew correction in point-to-point protocol packet
detection without data loss after baud... A system and method for affecting the behavior of the transmitting UART that, in turn, results in an internal state change in the receiving UART. The present... |
| US-6,381,702 |
Electronic clock A highly accurate electronic timepiece is provided in which the operation of a logical slowdown/speedup circuit for adjusting accuracy is controlled by a CPU.... |
| US-6,381,701 |
Method and device for time/date adjustment for computer A time/data adjustment device automatically synchronizes the time in a computer to the time information contained in signals from a broadcast satellite even when... |
| US-6,381,700 |
Remote network device for controlling the operation voltage of network
devices A method and apparatus for enhancing computer security while controllably enabling online remote access for power-up to a computer at a far cite and also... |
| US-6,381,699 |
Leak-resistant cryptographic method and apparatus The present invention provides a method and apparatus for securing cryptographic devices against attacks involving external monitoring and analysis. A... |
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