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Patent # Description
US-6,473,352 Semiconductor integrated circuit device having efficiently arranged link program circuitry
Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially...
US-6,473,351 Nanocapsules containing charged particles, their uses and methods of forming same
Nanomechanisms are employed in nanomemory elements which, in turn, are employable in nanoscale memory devices. A nanoscale particle is enclosed within a...
US-6,473,350 Semiconductor memory device having memory cell array structure with improved bit line precharge time and method...
A semiconductor memory device having a memory cell array structure and a precharging method, that improves bit line precharge time. The device has a common sense...
US-6,473,349 Cascode sense AMP and column select circuit and method of operation
A sense amplifier uses a cascode stage (76 or 100) that receives a predetermined bit line pair differential signal and provides an output. The cascode stage...
US-6,473,348 Data sensing circuit of semiconductor memory
A semiconductor memory device for performing an effective data sensing operation with a simple constitution. The device comprises first and second blocks each...
US-6,473,347 Semiconductor device having memory with effective precharging scheme
A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected...
US-6,473,346 Self burn-in circuit for semiconductor memory
An improved self burn-in circuit for a semiconductor memory generates a control signal, an address, and a test data for a burn-in test operation when a certain...
US-6,473,345 SEMICONDUCTOR MEMORY DEVICE WHICH CAN BE SIMULTANEOUSLY TESTED EVEN WHEN THE NUMBER OF SEMICONDUCTOR MEMORY...
At the time of writing data, a tester outputs a chip enable signal /CE of the L level and selection signals of the L level to simultaneously make semiconductor...
US-6,473,344 Semiconductor memory device capable of outputting a wordline voltage via an external pin
A semiconductor memory device includes a select signal generator, a wordline voltage generator, and a switch circuit. During a test operation mode, the device...
US-6,473,343 Signal amplification circuit for amplifying and sensing current difference and semiconductor memory device...
A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference...
US-6,473,342 Methods of operating split-gate type non-volatile memory cells
Methods of operating non-volatile memory cells (e.g., EEPROM devices) include the use of negative substrate biases during programming and erasing operations....
US-6,473,341 Method for programming EEPROM memory devices with improved reliability, and respective EEPROM memory device
The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a...
US-6,473,340 Reading method and circuit for a non-volatile memory
A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch...
US-6,473,339 Redundancy architecture for an interleaved memory
A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each...
US-6,473,338 Analog voltage supply circuit for a non-volatile memory
An electric circuit for writing an analog voltage to a non-volatile memory that improves accuracy of the write voltage and shortens the writing time of the...
US-6,473,337 Memory device having memory cells with magnetic tunnel junction and tunnel junction in series
A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can...
US-6,473,336 Magnetic memory device
A magnetic memory device comprises a memory cell assembled by first and second tunnel junction portions and a switch, each of the first and second tunnel...
US-6,473,335 MRAM configuration
A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two...
US-6,473,334 Multi-ported SRAM cell with shared bit and word lines and separate read and write ports
A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and...
US-6,473,333 Storage circuit with layered structure element
The present invention provides a circuit, in which a device typified by a PLED element is built into a flip-flop. In this case, a storage node of the device is...
US-6,473,332 Electrically variable multi-state resistance computing
An electrically operated, overwritable, multivalued, non-volatile resistive memory element is disclosed. The memory element includes a two terminal non-volatile...
US-6,473,331 Semiconductor memory device and various systems mounting them
A semiconductor memory device comprises a plurality of memory cells each having a source terminal and a drain terminal and a ferroelectric capacitor having a...
US-6,473,330 Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an...
A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a...
US-6,473,329 Semiconductor memory and method for accessing semiconductor memory
A semiconductor memory provided with ferroelectric layers, that includes memory cells, buffer cells, and buffer circuits. The memory cells each include a...
US-6,473,328 Three-dimensional magnetic memory array with a minimal number of access conductors therein
A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory...
US-6,473,327 Semiconductor memory having a pair of bank select drivers driving each bank select line
A semiconductor memory comprises a memory cell array having a plurality of rows and a plurality of columns, a plurality of word lines each connected to a gate of...
US-6,473,326 Memory structures having selectively disabled portions for power conservation
An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may...
US-6,473,325 Bit line sensing control circuit for a semiconductor memory device and layout of the same
A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is...
US-6,473,324 Layout of a sense amplifier with accelerated signal evaluation
A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in...
US-6,473,323 Device for transferring energy to a transformer secondary during a predetermined time period
A device for transferring power by an electrical energy transformer, and in particular by a magnetic coupler, including on a primary side a primary winding in...
US-6,473,322 AC-DC converter
In an upconverter comprising a choke, a switching element and a diode, the switching element is controlled in such a way that the time interval during which the...
US-6,473,321 Semiconductor integrated circuit and nonvolatile semiconductor memory
For a semiconductor integrated circuit having an internal booster circuit such as a flash memory, voltage booster circuits capable of generating a boosted...
US-6,473,320 Voltage converter circuit with self-oscillating half-bridge configuration and with protection against hard...
The voltage converter circuit has first and second input terminals, and first and second output nodes, and comprises: a first power switch connected between the...
US-6,473,319 Plant for transmitting electric power and a method for changing the direction of power transmission in such a plant
A plant for transmitting electric power with a direct voltage network and at least two stations connected thereto with line commutated valves (15, 16) with...
US-6,473,318 Leakage energy recovering system and method for flyback converter
An switching converter, having a transformer having primary, secondary and auxiliary windings, an actively controlled switch, a capacitor and a first passive...
US-6,473,317 Forward DC/DC converter with semi-synchronous rectification and improved efficiency
A forward DC/DC converter using semi-synchronous MOSFET rectifiers with a peak detector and a pulse transformer. In another example edge triggered circuits and...
US-6,473,316 Phase control circuit and switching regulator
A phase control circuit which can stabilize voltage control when used in a switching regulator, and a switching regulator using such a phase control circuit are...
US-6,473,315 Telecommunications equipment transportation apparatus
The telecommunications equipment transportation apparatus of the present invention is comprised of components including a base section, a container section and a...
US-6,473,314 RF power amplifier assembly employing multi-layer RF blocking filter
A low cost radio frequency interference filter assembly comprises a multiple layer structure including a middle trace layer disposed between an upper ground...
US-6,473,313 Fastening device for a securing data storage device
A fastening device for securing a data storage device (50) with a screw (52) secured thereon includes a locating plate (10) and a bracket (26). The bracket...
US-6,473,312 Printed circuit board, printed circuit board module and electronic device adapting same
A printed circuit board includes a ground layer, a power supply layer divided into a plurality of lands, a dielectric layer disposed so as to cover the plurality...
US-6,473,311 Gate area relief strip for a molded I/C package
A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a...
US-6,473,310 Insulated power multichip package
The invention includes a multichip integrated circuit package having at least two chips electrically isolated from one another. Within the multichip integrated...
US-6,473,309 Apparatus and method for mounting a motherboard to a computer chassis
A method and apparatus for mounting a motherboard to a computer chassis wherein the motherboard includes a first integrated fastener member and the chassis...
US-6,473,308 Stackable chip package with flex carrier
A stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar...
US-6,473,307 Method and apparatus for efficient electronics positioning and connection systems
The present invention provides a method and apparatus for efficient electronics positioning and connection systems. In one embodiment of the present invention,...
US-6,473,306 Heat sink assembly retainer for electronic integrated circuit package
A retainer device (1) for fastening a heat sink (2) to a printed circuit board module (3). The heat sink comprises a base plate (22) and a plurality of upwardly...
US-6,473,305 Fastening system and method of retaining temperature control devices used on semiconductor dies
A fastening system and a method for retaining temperature control devices used on semiconductor dies transfers the load of the temperature control devices around...
US-6,473,304 Thermally conductive case for electrical components and method of manufacture therefor
A power supply and a method of manufacture therefor. The power supply includes a circuit board containing conductors for interconnecting electrical components of...
US-6,473,303 Cooling device for a high-power semiconductor module
A cooling device for a high-power semiconductor module has a cooler lower part (1) and a cooler upper part (2), with the cooler upper part (2) being connected to...
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