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| Patent # | Description |
|---|---|
| US-6,473,853 |
Method and apparatus for initializing a computer system that includes
disabling the masking of a maskable... A method of securing a boot process for a computer system enables a processor to boot from a location identified by a boot vector. The method includes the step... |
| US-6,473,852 |
Method and circuit for performing automatic power on reset of an integrated
circuit Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust... |
| US-6,473,851 |
System for combining plurality of input control policies to provide a
compositional output control policy Method and apparatus for combining a plurality of overlapping policy-based controllers. System also applicable to policy-based process servers. System combines... |
| US-6,473,850 |
System and method for handling instructions occurring after an ISYNC
instruction An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC... |
| US-6,473,849 |
Implementing locks in a distributed processing system A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using... |
| US-6,473,848 |
Method for controlling memory access on a machine with non-uniform memory
access and machine for implementing... On a machine with non-uniform memory access distributed over several modules, each module includes one or more processors for executing tasks on a virtual or... |
| US-6,473,847 |
Memory management method for use in computer system The present invention is directed to a method for managing memory in a computer whereby memory is divided into a first and a second section, and whereby the... |
| US-6,473,846 |
Content addressable memory (CAM) engine A content addressable memory ("CAM") engine or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known,... |
| US-6,473,845 |
System and method for dynamically updating memory address mappings In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus... |
| US-6,473,844 |
System and method to protect vital memory space from non-malicious writes
in a multi domain system A system and method is described in which protected memory writes are achieved in single transaction without leaving open a window in time for erroneous data to... |
| US-6,473,843 |
Alternate access mechanism for saving and restoring state of write-only
register The present invention relates to a method and apparatus for restoring a status data in a computer system. The circuit comprises: a read-only register for storing... |
| US-6,473,842 |
Virtual memory managing system for managing swap-outs by page units and a
batch swap-out by task units The virtual memory managing system of the present invention includes a virtual memory managing unit that manages a virtual memory system by combining swap-out in... |
| US-6,473,841 |
Signal processing apparatus with memory access history storage In a signal processing apparatus having a memory and plural blocks for accessing the memory provided in an LSI, for the ease of cause analysis in the event of a... |
| US-6,473,840 |
Data processing system having a network and method for managing memory by
storing discardable pages in a local... A method in a data processing system for managing memory within the data processing system. A discardable page that is to be removed from the memory is... |
| US-6,473,839 |
Device for exchanging data and process for operating it A device or arrangement for exchanging data between a main station (master) (10) and at least one secondary station (slave) (12, 12n), which each have access to... |
| US-6,473,838 |
Data transfer system for multiple network processors using dual DRAM
storage The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In... |
| US-6,473,837 |
Snoop resynchronization mechanism to preserve read ordering A processor employing a post-cache (LS2) buffer. Loads are stored into the LS2 buffer after probing the data cache. The load/store unit snoops the loads in the... |
| US-6,473,836 |
Computing system and cache memory control apparatus controlling prefetch in
hierarchical cache memories A cache memory control apparatus provided to prevent necessary data from being ejected from hierarchical cache memories and to avoid conflicts of process in the... |
| US-6,473,835 |
Partition of on-chip memory buffer for cache A data cache is constructed with the same dimensions as for a conventional n-way associative cache, but is constructed as an (n-1)-way associative cache, so that... |
| US-6,473,834 |
Method and apparatus for prevent stalling of cache reads during return of
multiple data words In a data processing system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and... |
| US-6,473,833 |
Integrated cache and directory structure for multi-level caches A method of operating a multi-level memory hierarchy of a computer system and an apparatus embodying the method, wherein multiple levels of storage subsystems... |
| US-6,473,832 |
Load/store unit having pre-cache and post-cache queues for low latency load
memory operations A processor has pre-cache and post-cache buffers. The pre-cache (or LS1) buffer stores memory operations which have not yet probed the data cache. The post-cache... |
| US-6,473,831 |
Method and system for providing universal memory bus and module A memory card in accordance with the present invention allows a variety of memory devices to interface with a processor. The memory card comprises a data base... |
| US-6,473,830 |
System and method for organizing data stored in a log structured array In a storage system comprising an array of storage devices, including a processor and memory, a plurality of logical tracks are organized on the storage devices... |
| US-6,473,829 |
Data storage device providing communication between processing units A system and method, employing a data storage device, for providing communication between a plurality of processing units which are respectively unconnected to... |
| US-6,473,828 |
Virtual channel synchronous dynamic random access memory According to one embodiment, a virtual channel synchronous dynamic random access memory (VCSDRAM) (100) can perform a high-frequency test with lower frequency... |
| US-6,473,827 |
Distributed multi-fabric interconnect An interconnect network having a plurality of identical fabrics partitions the switching elements of the fabrics, so that many links can be combined into single... |
| US-6,473,826 |
PCI delayed transaction time out counter and associated methods The invention provides for clearing a delayed transaction buffer associated with master-to-slave transactions on a PCI bus. In a slave such as a PCI bridge chip,... |
| US-6,473,825 |
Apparatus and method for controlling secure communications between
peripheral components on computer buses... An apparatus for and a method of controlling secure communication between peripheral components in a communication system. The security level of each peripheral... |
| US-6,473,824 |
Dynamic association of input/output device with application programs An object-oriented framework is introduced for coupling device drivers to an application program. Two class trees are introduced: the first class tree comprises... |
| US-6,473,823 |
Method and apparatus for common thin-client NC and fat-client PC
motherboard and mechanicals Components and circuitry, including a common microprocessor, are combined into a single motherboard that is common to both a Personal Computer (PC) and a Network... |
| US-6,473,822 |
Digital signal processing apparatus A digital signal processing apparatus for processing a plurality of video signals and a plurality of audio signals is provided, and comprises a computer... |
| US-6,473,821 |
Multiple processor interface, synchronization, and arbitration scheme using
time multiplexed shared memory for... An arbitration and synchronization method and system for allowing multiple processors to access a shared memory includes an arbitrator. The arbitrator is... |
| US-6,473,820 |
Method and apparatus for user level monitor implementation Methods and apparatus for implementing an atomic monitor wait operation are disclosed. According to one aspect of the present invention, a computer-implemented... |
| US-6,473,819 |
Scalable interruptible queue locks for shared-memory multiprocessor A method for a computation agent to acquire a queue lock in a multiprocessor system that prevents deadlock between the computation agent and external interrupts.... |
| US-6,473,818 |
Apparatus and method in a network interface device for asynchronously
generating SRAM full and empty flags... A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host... |
| US-6,473,817 |
Method and apparatus for efficient bus arbitration A bus arbitration regulates access to a common bus by a plurality of devices by assigning each device a priority rank. A current weighted bandwidth of each... |
| US-6,473,816 |
Apparatus and method for determining bus use right In order to efficiently utilize a bus system, when a new job occurs, the preferences assigned to jobs is determined in accordance with the volumes of the data... |
| US-6,473,815 |
Queue sharing This invention provides queue sharing methods and apparatus of a queuing system which includes queues of multiple priorities or classes. When data is received in... |
| US-6,473,814 |
System for optimally tuning a burst length by setting a maximum burst
length based on a latency timer value and... A method and system for choosing an optimal PCI adapter burst length is disclosed. The optimal burst length is automatically determined by the adapter... |
| US-6,473,813 |
Module based address translation arrangement and transaction offloading in
a digital system An address translation arrangement and associated method for use in a digital system are described. The system includes a plurality of modules and a bus... |
| US-6,473,812 |
System using internet email for communicating status information from
business office printing device when it... A method and system for monitoring, controlling and diagnosing operation of a machine such as a business office machine including a facsimile machine, a copier,... |
| US-6,473,811 |
Method and apparatus for displaying a connection status of a device based
on connection information An information processing apparatus to which a plurality of devices are connected comprises: an obtaining means for obtaining system setting information provided... |
| US-6,473,810 |
Circuits, systems, and methods for efficient wake up of peripheral
component interconnect controller A controller (20.sub.3) for coupling between a computer bus (20) and one or more units (22.sub.1, 22.sub.2) compatible with the bus. The controller comprises a... |
| US-6,473,809 |
Scheduling method and apparatus for network-attached storage devices and
other systems A computer-implemented scheduling method and apparatus for scheduling operations relating to a predetermined activity. The activity includes scheduling... |
| US-6,473,808 |
High performance communication controller for processing high speed data
streams wherein execution of a task... A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two... |
| US-6,473,807 |
System for invocation of CICS programs as database stored procedures Novel techniques for operating a transactional processing system on which a CICS progran is stored. The CICS program includes logic for implementing business... |
| US-6,473,806 |
Methods and apparatus for managing objects and processes in a distributed
object operating environment A variety of methods and apparatus for managing deactivation and deletion of objects and server processes are taught. According to some embodiments of the... |
| US-6,473,805 |
Method and apparatus for intergrating wireless and non-wireless devices
into an enterprise computer network... In an enterprise network system a plurality of software systems are integrated using an enterprise wide software management system and communicate with a... |
| US-6,473,804 |
System for indexical triggers in enhanced video productions by redirecting
request to newly generated URI based... Disclosed are a method apparatus and system for providing addressed network content in connection with a video production. A disclosed method includes receiving... |
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