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| Patent # | Description |
|---|---|
| US-6,472,952 |
Antenna duplexer circuit with a phase shifter on the receive side A high frequency wireless circuit apparatus is formed by connecting a phase shifter between an antenna duplexer and a low noise amplifier, so that the impedance... |
| US-6,472,951 |
Microwave multiplexer with manifold spacing adjustment A series of tuning brackets are mounted on the microwave waveguide manifold at positions between the input waveguide/filter couplings. These brackets constrain... |
| US-6,472,950 |
Broadband coupled-line power combiner/divider A broadband coupled-line N-way power combiner is presented for combining N RF signals into a common load. This combiner includes N.gtoreq.2 input ports, a common... |
| US-6,472,949 |
Signal attenuators A signal attenuator may have a first attenuator (1t) and a second attenuator (2t). The first attenuator (1t) is a .pi.-type resistance attenuator and includes... |
| US-6,472,948 |
High-power precision 1 dB step attenuator A step attenuator for use in attenuating an electromagnetic signal. The step attenuator includes a first path having a plurality of attenuator structures... |
| US-6,472,947 |
Multiple signal path antenna circuit having differential attenuation
between signal paths An antenna circuit is described which makes it possible to suppress intermodulation products. This antenna circuit includes an antenna connection device to which... |
| US-6,472,946 |
Modulation circuit and image display using the same A modulation circuit and an image display able to be set to match the relation of luminance data and a luminance of a LED with a .gamma.-characteristic of a CRT... |
| US-6,472,945 |
Operational amplifier oscillator An operational amplifier oscillator uses an operational amplifier as a low impedance driver for a resonator, the output from the operational amplifier being a... |
| US-6,472,944 |
Voltage controlled oscillator with delay circuits A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a... |
| US-6,472,943 |
Oscillating circuit and method for calibrating same An oscillating circuit (10) includes a quartz crystal oscillator (12) for generating a clock signal (20). The clock signal is synchronized to a master signal... |
| US-6,472,942 |
Parasitically compensated resistor for integrated circuits A parasitically compensated resistor (50) for integrated circuits includes a substrate (52). A polysilicon resistor (54) is formed in the substrate (52). The... |
| US-6,472,941 |
Distributed amplifier with terminating circuit capable of improving gain
flatness at low frequencies A plurality of amplifying circuits 31 to 34 are connected between input and output transmission circuits 10 and 20 in a forward direction, a bias-T 29 is... |
| US-6,472,940 |
Gigabit ethernet transceiver with analog front end Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain... |
| US-6,472,939 |
Low power supply CMOS differential amplifier topology A structure and method for improving differential amplifier operation is provided. High performance, wide bandwidth or very fast CMOS amplifiers are possible... |
| US-6,472,938 |
Automatic level controlling circuit In an automatic level controlling circuit, an output from a full-wave rectifying circuit 12 is supplied to a first and a second time constant circuit. The first... |
| US-6,472,937 |
Bias enhancement circuit for linear amplifiers The invention includes an amplifier and a biasing circuit. The amplifier may have one or more driver stages and a final stage. Each stage may be connected in... |
| US-6,472,936 |
Low-noise gain switching circuit using tapped inductor There is disclosed an improved variable gain low-noise amplifier. The variable gain low-noise amplifier comprises: 1) an input transistor having a first ground... |
| US-6,472,935 |
Combining networks for switchable path power amplifiers The present invention teaches a power amplifier having two or more output power devices and a combining network for switching the output path between these... |
| US-6,472,934 |
Triple class E Doherty amplifier topology for high efficiency signal
transmitters A Doherty amplifier circuit is provided comprising at least three class E amplifiers receiving separated amplitude and phase information from at least one signal... |
| US-6,472,933 |
Switching amplifier incorporating return-to-zero quaternary power switch Invention resides in a switching amplifier having a quaternary input control signal that provides quaternary levels (1, 0H, -1, and 0L) which is coupled to an... |
| US-6,472,932 |
Transconductor and filter circuit A transconductor which has a transconductance gm and which receives an input voltage V.sub.In and outputs in response to the input voltage V.sub.in an output... |
| US-6,472,931 |
Method and apparatus that models neural transmission to amplify a
capacitively-coupled input signal One embodiment of the present invention provides a system for amplifying an input signal received from a capacitive sensor. The system includes an input for... |
| US-6,472,930 |
Semiconductor integrated circuit device A current generator (CG) is composed of a constant-current-source transistor M1, and transistors (M2, M3). On receipt of control signals (VG2, VG3) respectively... |
| US-6,472,929 |
Semiconductor device A semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size. The... |
| US-6,472,928 |
Reduced noise band gap reference with current feedback and method of using A band gap reference (32) provides low noise operation utilizing capacitor (98) to produce a low pass filter operating with high impedance node (104). Increased... |
| US-6,472,927 |
Circuit having increased noise immunity and capable of generating a
reference voltage or terminating a... A voltage divider suppresses noise in a voltage divider output by filtering the voltages at the gate terminals of the transistors that comprise a voltage... |
| US-6,472,926 |
Internal voltage generation circuit A plurality of pump modules are provided, the number of pump modules to be activated is changed depending on a mode of operation, and the number of pump modules... |
| US-6,472,925 |
Mixer circuit with negative feedback filtering A mixer circuit having a high conversion gain which is excellent in linearity comprises an amplifier (1A) for amplifying one of two signals to be mixed with each... |
| US-6,472,924 |
Integrated semiconductor circuit having analog and logic circuits In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or... |
| US-6,472,923 |
Semiconductor device A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first... |
| US-6,472,922 |
System and method for flexibly distributing timing signals The present invention comprises a system and method for flexibly distributing timing signals. Timing signals may require varying delays when connected, via... |
| US-6,472,921 |
Delivering a fine delay stage for a delay locked loop A circuit, for use in a delay locked loop, provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current... |
| US-6,472,920 |
High speed latch circuit A latch circuit having reduced propagation delay and set-up and hold times comprises at least one set of cross-coupled transistor devices arranged between an... |
| US-6,472,919 |
Low voltage latch with uniform stack height Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the... |
| US-6,472,918 |
Self-referencing slicer method and apparatus for high-accuracy clock duty
cycle generation A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value... |
| US-6,472,917 |
Semiconductor integrated circuit device having compensation for wiring
distance delays A third gate circuit which is controlled by a clock signal and operates upon the detection of change of a signal on a critical path driven by a first gate... |
| US-6,472,916 |
Semiconductor integrated circuit device and microcomputer A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation... |
| US-6,472,915 |
Method for charge pump tri-state and power down/up sequence without
disturbing the output filter An apparatus comprising a phase lock loop (PLL) and a charge pump. The PLL may be configured to generate an output signal in response to an input signal. The... |
| US-6,472,914 |
Process independent ultralow charge pump The charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop is disclosed... |
| US-6,472,913 |
Method and apparatus for data sampling A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are... |
| US-6,472,912 |
Device for power supply detection and power on reset A circuit for power supply detection and power on reset. The circuit comprises two separate component groups for producing separate currents which vary in... |
| US-6,472,911 |
Output buffer circuit of semiconductor integrated circuit An output buffer circuit for a logical integrated circuit in which the peak value of switching noise is small thereby reducing the possibility of malfunctions. A... |
| US-6,472,910 |
Electrical load driving device An electrical load driving device is constructed to accurately detect an over-current state in either a high-side output mode or a low-side output mode... |
| US-6,472,909 |
Clock routing circuit with fast glitchless switching A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with... |
| US-6,472,908 |
Differential output driver circuit and method for same An output circuit is provided which exhibits a waveform having a higher edge rate, with less ringing and power consumption than many conventional differential... |
| US-6,472,907 |
Input buffer of a semiconductor device that gives only a small scattering
in delay time In a semiconductor memory device, its clock buffer includes a first comparator having a pair of P channel MOS transistors whose gates receive a clock signal and... |
| US-6,472,906 |
Open drain driver having enhanced immunity to I/O ground noise An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor... |
| US-6,472,905 |
Voltage level translator A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The... |
| US-6,472,904 |
Double data rate input and output in a programmable logic device A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide... |
| US-6,472,903 |
Programmable logic device input/output architecture with power bus
segmentation for multiple I/O standards In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic... |
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