Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-6,493,277 |
Data generation circuit and method for data generating A data generating circuit includes a memory which writes picture data into a plurality of storage areas and reads the picture data from the plurality of storage... |
| US-6,493,276 |
Word line boost circuit An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating... |
| US-6,493,275 |
Semiconductor integrated circuit device and electronic equipment Each inverter includes any of a P-channel modulation MOS transistor, a normal N-channel MOS transistor, a normal P-channel MOS transistor, and an N-channel... |
| US-6,493,274 |
Data transfer circuit and semiconductor integrated circuit having the same Disclosed is a low-power data transfer circuit having a high data transfer rate. This data transfer circuit of the invention includes a first selection circuit... |
| US-6,493,273 |
Semiconductor memory having electrically erasable and programmable
nonvolatile semiconductor memory cells A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section... |
| US-6,493,272 |
Data holding circuit having backup function A data holding circuit that retreats and restores internal statuses. The data holding portion includes a memory. At least one internal state of the data holding... |
| US-6,493,271 |
Data line disturbance free memory block divided flash memory and
microcomputer having flash memory therein A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells... |
| US-6,493,270 |
Leakage detection in programming algorithm for a flash memory device Leakage detection in a programming algorithm for a flash memory device. According to one embodiment of the present invention a method includes programming a... |
| US-6,493,269 |
Dual cell reading and writing technique The cells of a memory cell array are programmed in a pair wise manner. The pairs are separated by at least one memory cell, reducing the possibility of... |
| US-6,493,268 |
Circuit device for performing hierarchic row decoding in non-volatile
memory devices A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory... |
| US-6,493,267 |
Nonvolatile semiconductor memory device having verify function A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the... |
| US-6,493,266 |
Soft program and soft program verify of the core cells in flash memory
array A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and... |
| US-6,493,265 |
Nonvolatile semiconductor memory device A method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential,... |
| US-6,493,264 |
Nonvolatile semiconductor memory, method of reading from and writing to the
same and method of manufacturing... A nonvolatile semiconductor memory including at least two cells each comprising: a floating gate formed on a semiconductor substrate with the intervention of a... |
| US-6,493,263 |
Semiconductor computing circuit and computing apparatus Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an... |
| US-6,493,262 |
Method for operating nonvolatile memory cells The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile... |
| US-6,493,261 |
Single bit array edges Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of... |
| US-6,493,260 |
Nonvolatile memory device, having parts with different access time,
reliability, and capacity The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a... |
| US-6,493,259 |
Pulse write techniques for magneto-resistive memories A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively... |
| US-6,493,258 |
Magneto-resistive memory array A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory... |
| US-6,493,257 |
CMOS state saving latch A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch... |
| US-6,493,256 |
Semiconductor memory device A gate of an NMOS transistor (N1) is connected to a memory terminal (Na) and a gate of an NMOS transistor (N2) is connected to a memory terminal (Nb). Sources of... |
| US-6,493,255 |
Semiconductor integrated circuit device and information processing device
employing semiconductor integrated... A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is provided. Adjacent 1-bit memory values and a... |
| US-6,493,254 |
Current leakage reduction for loaded bit-lines in on-chip memory structures Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access... |
| US-6,493,253 |
DRAM memory cell A DRAM memory cell includes a storage capacitor device with two storage capacitors connected in parallel with one another. One of the storage capacitors is a... |
| US-6,493,252 |
Selective device coupling Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods... |
| US-6,493,251 |
Ferroelectric memory device A series connected unit type ferroelectric memory device is provided, in which a substantially constant read signal margin can be obtained regardless of the... |
| US-6,493,250 |
Multi-tier point-to-point buffered memory interface Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller... |
| US-6,493,249 |
Semiconductor apparatus, power converter and automobile A semiconductor apparatus includes positive and negative side conductors for bridge-connecting semiconductor switches, constituted to a wide conductor, and... |
| US-6,493,248 |
Relating to inverters An inverter charger, fed with d.c. from a battery, to supply a.c. to a load, comprising eight inverters stages which each provide an alternating step function... |
| US-6,493,246 |
Power conversion with stop conversion during low integrated power
conditions In a solar power generation apparatus, when power necessary for a control circuit and the like is supplied from the load side of an inverter, a period from when... |
| US-6,493,245 |
Inrush current control for AC to DC converters The present invention provides for an apparatus and corresponding method for controlling inrush current in an AC-DC power converter by controlling the state of a... |
| US-6,493,244 |
System with massive choke in parallel with a/c line for load conditioning A massive choke coil [e.g. exceeding about three henries, with at least a thousand turns and a relatively low internal resistance of about eleven ohms] placed in... |
| US-6,493,243 |
Redundant power system and power supply therefor A redundant power system includes plural load-sharing power supplies connected to a common AC output bus. Identical circuitry is provided in each supply to... |
| US-6,493,242 |
Power factor controller A drive with a high impedance input, low impedance output is created. When a switching or driving action requiring the sourcing and sinking of current from a... |
| US-6,493,241 |
EMI protective spring plate for motherboard An EMI protective spring plate having an oblique supporting portion diagonally connected between a flat top contact portion and a flat bottom soldering portion,... |
| US-6,493,240 |
Interposer for connecting two substrates and resulting assembly The present invention is an interposer for electrically coupling a microcard with a mother board. The interposer includes a frame which is interposed between the... |
| US-6,493,239 |
Arrangement of memory-card accomodating portions in a recording and
reproducing apparatus An arrangement of memory-card accommodating portions in a recording and reproducing apparatus includes a plurality of card slots for respectively accommodating... |
| US-6,493,238 |
Method and apparatus to compliantly interconnect area grid arrays and
printed wiring boards A method and system of utilizing inexpensively manufactured, electrically conductive and mechanically compliant disks to interconnect an area grid array ("AGA")... |
| US-6,493,237 |
Pressure sensor housing A novel pressure sensor housing configuration and method of assembly are described. A pressure transducer including a tube for measuring pressure and leads for... |
| US-6,493,236 |
Electronic equipment An electronic equipment enclosure has a lower housing part and a main board fixed relative thereto. A main board connector is fixed to the main board and faces... |
| US-6,493,235 |
Auto docking/locking rack hardware for easy serviceability of printed
circuit cards in tight spaces A guide structure and matching printed circuit card carrying cartridge provides hot pluggability functionality even when electronic circuit components need to be... |
| US-6,493,234 |
Electronic components mounting structure According to the present invention, there is provided an electronic components mounting structure constituted by a plurality of electronic components having lead... |
| US-6,493,233 |
PCB-to-chassis mounting schemes A method and assembly for mounting printed circuit boards (PCBs) to a chassis. In one embodiment, a plurality of internally-threaded mounting posts are secured... |
| US-6,493,232 |
Housing for an electronic control device in vehicles A housing for an electronic control device in vehicles comprises a bottom part (10) which has a metallic baseplate (12), and a cover part (14) made of plastic.... |
| US-6,493,231 |
Electrical apparatus A housing for a microwave circuit is formed from a base made of metal matrix composite material and walls made of sheet metal. The base and the walls are joined... |
| US-6,493,230 |
Modular computer system mechanical interconnection A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis... |
| US-6,493,229 |
Heat sink chip package The present invention relates to enhanced thermal management of a microelectronic device package on a printed circuit board (PCB) having a solder ring or dam... |
| US-6,493,228 |
Heat radiation packaging structure for an electric part and packaging
method thereof A heat radiation packaging structure without getting a board itself larger, but with an excellent heat radiation ability and a low cost is provided. A bus bar 12... |
| US-6,493,227 |
Cooling apparatus for power semiconductors A cooling apparatus for power semiconductors, which apparatus is essentially box-shaped, has two extruded cooling sections (14, 15) joined to each other. One of... |
Copyright 2008−2012 Patents.com
