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| Patent # | Description |
|---|---|
| US-6,493,828 |
Information processing apparatus, information processing method, and
program storage medium Disclosed herein are an information processing apparatus, an information processing method, and a program storage medium that allow a user to quickly capture an... |
| US-6,493,827 |
Method and system for monitoring configuration changes in a data processing
system A method and system for monitoring and adapting to configuration changes in a data processing system having a known configuration, while power is applied... |
| US-6,493,826 |
Method and system for fault tolerant transaction-oriented data processing
system A fault-tolerant transaction processing system and method stores records associated with operations of the system in order to permit recovery in the event of a... |
| US-6,493,825 |
Authentication of a host processor requesting service in a data processing
network An object is authenticated by transmitting a random number to the object. The object has an integrated circuit chip including a memory and encryption circuitry.... |
| US-6,493,824 |
Secure system for remotely waking a computer in a power-down state A secure system and method is provided for remotely waking a computer from a power down state. In one embodiment, a network interface card receives incoming data... |
| US-6,493,823 |
Instrument for making secure data exchanges An instrument for making secure messages exchanged between each of the actors of a network having a plurality of actors, each being capable of acting as a sender... |
| US-6,493,822 |
Foreign drive determination and drive letter conflict resolution A programable apparatus and method for assigning drive letters without conflicts to resource devices in a data processing system based upon three signature... |
| US-6,493,821 |
Recovery from writeback stage event signal or micro-branch misprediction
using instruction sequence number... A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an... |
| US-6,493,820 |
Processor having multiple program counters and trace buffers outside an
execution pipeline In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the... |
| US-6,493,819 |
Merging narrow register for resolution of data dependencies when updating a
portion of a register in a... A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which... |
| US-6,493,818 |
Technique for pipelining synchronization to maintain throughput across two
asynchronous clock domain boundaries This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock... |
| US-6,493,817 |
Floating-point unit which utilizes standard MAC units for performing SIMD
operations The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point... |
| US-6,493,816 |
Method and apparatus for encapsulating address translation for shared
persistent virtual storage A preferred embodiment of the present invention provides an intelligent reference object (IRO), which is used to encapsulate address translation between shared... |
| US-6,493,815 |
Interleaving/deinterleaving device and method for communication system An interleaving method comprises storing input data in a memory according to a sequential address; providing a virtual address determined by adding a... |
| US-6,493,814 |
Reducing resource collisions associated with memory units in a multi-level
hierarchy memory system A system and method for reducing resource collisions associated with memory units. Resource collisions may be reduced in part by a hash that combines the number... |
| US-6,493,813 |
Method for forming a hashing code A method of forming a hashing code includes the steps of: first selecting a first linear feedback transform generator that is perfect over a first range. A... |
| US-6,493,812 |
Apparatus and method for virtual address aliasing and multiple page size
support in a computer system having a... A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support... |
| US-6,493,811 |
Intelligent controller accessed through addressable virtual space File operations on files in a peripheral system are controlled by an intelligent controller with a file processor. The files are accessed as if the intelligent... |
| US-6,493,810 |
Method and system for allocating cache memory for a network database
service A method is provided for estimating the size of cache memory required for optimal performance of a network database service, such as a directory service, by... |
| US-6,493,809 |
Maintaining order of write operations in a multiprocessor for memory
consistency A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The... |
| US-6,493,808 |
Device and process for testing a reprogrammable nonvolatile memory The invention relates to a device for testing a reprogramable non-volatile memory having dedicated areas protectable in reading, writing and/or erasing and whose... |
| US-6,493,807 |
Updating flash blocks The present invention is a system and method for updating memory. The contents of a first storage location in a plurality of storage locations are first copied... |
| US-6,493,806 |
Method and apparatus for generating a transportable physical level data
block trace A system and method for generating a transportable physical level data block trace for a computer system. The method comprises capturing a first physical level... |
| US-6,493,805 |
Method and system for synchronizing block-organized data transfer amongst a
plurality of producer and consumer... With respect to a particular facility semaphore-based synchronizing is executed among a first station and one or more second stations. For each station a single... |
| US-6,493,804 |
Global file system and data storage device locks A system includes shared Small Computer System Interface (SCSI) storage devices for processing clients coupled by a fiber channel interface. The storage devices... |
| US-6,493,803 |
Direct memory access controller with channel width configurability support A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA... |
| US-6,493,802 |
Method and apparatus for performing speculative memory fills into a
microprocessor According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present... |
| US-6,493,801 |
Adaptive dirty-block purging An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of... |
| US-6,493,800 |
Method and system for dynamically partitioning a shared cache A cache memory shared among a plurality of separate, disjoint entities each having a disjoint address space, includes a cache segregator for dynamically... |
| US-6,493,799 |
Word selection logic to implement an 80 or 96-bit cache SRAM A logic which enables implementation of a 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by... |
| US-6,493,798 |
Upgradeable cache circuit using high speed multiplexer An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a... |
| US-6,493,797 |
Multi-tag system and method for cache read/write A method and device are provided for reading data from a trace cache in a manner that reduces the time and power consumed by such an operation. A mini-tag is... |
| US-6,493,796 |
Method and apparatus for maintaining consistency of data stored in a group
of mirroring devices In one embodiment, mirroring communication from a second source storage device to a second target storage device in a data mirroring system is disabled when... |
| US-6,493,795 |
Data storage system A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a... |
| US-6,493,794 |
Large scale FIFO circuit In a large scale FIFO circuit comprising a shift register circuit, the shift register circuit is reduced in its occupation area size to reduce the entire size of... |
| US-6,493,793 |
Content addressable memory device having selective cascade logic and method
for selectively combining match... A content addressable memory (CAM) device having an array including a plurality of rows of CAM cells each coupled to a match line; match flag logic having inputs... |
| US-6,493,792 |
Mechanism for broadside reads of CAM structures A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted... |
| US-6,493,791 |
Prioritized content addressable memory A prioritized content addressable memory having an at most one hit property despite the presence of redundant values stored therein. Redundant values within the... |
| US-6,493,790 |
Translation-lookaside buffer with current tracking reference circuit A translation-lookaside buffer includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a... |
| US-6,493,789 |
Memory device which receives write masking and automatic precharge
information A semiconductor memory device which includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive... |
| US-6,493,788 |
Processor with embedded in-circuit programming structures An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself; as well... |
| US-6,493,787 |
Device, system and method for accessing plate-shaped memory A drive apparatus wherein a plurality of media each including a memory element can be successively accessed to continuously write and/or read out data into... |
| US-6,493,786 |
Integrated network switching hub and bus structure A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of que switch transistors, source to drain for data... |
| US-6,493,785 |
Communication mode between SCSI devices The present invention relates to a method of in-band communication, outside the standard SCSI communication protocol, between SCSI bus repeaters and initiator... |
| US-6,493,784 |
Communication device, multiple bus control device and LSI for controlling
multiple bus The present invention provides a multiple bus control device and others which can also be applied to access control by a signal having a directional propagation... |
| US-6,493,783 |
Undocking method for multilayer-dock structure constituted by docking
plurality of expansion units to a portable PC Described is an improved method for undocking a structure having an optional number of tiers from a multilayer-dock structure constituted by docking a plurality... |
| US-6,493,782 |
Method for performing hot docking of a portable computer into a docking
station A method and apparatus for allowing hot docking of a portable computer (15) into a docking station (20) comprising the steps of making a physical connection... |
| US-6,493,781 |
Servicing of interrupts with stored and restored flags A method is provided for avoiding the corruption of information which can occur when a processor nests subroutines and these subroutines disable and enable... |
| US-6,493,780 |
Wake-up-on-ring power conservation for host signal processing communication
system An communication system such as a host signal processing modem includes a host computer and a device that is coupled to communication lines and a host processor... |
| US-6,493,779 |
Method and system for interrupt handling using device pipelined packet
transfers A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase.... |
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