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| Patent # | Description |
|---|---|
| US-6,492,874 |
Active bias circuit An active bias circuit 30 connected to a power amplifier PA maintains a power amplifier DC quiescent current at a fixed value over a wide temperature range. The... |
| US-6,492,873 |
Method of distributed amplifier design utilizing filter synthesis
techniques The present invention describes the method and system of applying filter synthesis technique to distributed amplifier design. The method for synthesizing a... |
| US-6,492,872 |
High frequency power amplifying module and wireless communication apparatus A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power... |
| US-6,492,871 |
Current feedback operational amplifier The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the... |
| US-6,492,870 |
Class AB, high speed, input stage with base current compensation for fast
settling time The improved Class AB input stage monitors the needs of base current in the slewing transistors 22-25 and supplies that base current with extremely fast and... |
| US-6,492,869 |
Linear amplifier and radio communication apparatus using the same A linear amplifier comprises a first current-mirror circuit including a first transistor whose base and collector are short-circuited for diode connection and... |
| US-6,492,868 |
Dynamic range enhancement technique Apparatus and methods are disclosed for adding minimum pulse widths to the coarse resolution output of a multi-reference switching amplifier. This acts to null... |
| US-6,492,867 |
Method and apparatus for improving the efficiency of power amplifiers,
operating under a large peak-to-average... Method and apparatus for improving the efficiency and the dynamic range of a power amplifier operated with signals having a large peak-to-average ratio. A... |
| US-6,492,866 |
Electronic circuit with bulk biasing for providing accurate electronically
controlled resistance A circuit arrangement for generating an electronically controlled electrical resistance by apparatus of at least one MOS transistor. A source-drain junction of... |
| US-6,492,865 |
Band pass filter from two filters A band pass filter includes a pair of filters having different center frequencies and a difference amplifier coupled to the outputs of the filters. The filters... |
| US-6,492,864 |
Circuit configuration for low-power reference voltage generation A circuit configuration for low-power reference voltage generation, is described. The circuit has a programmable voltage source which generates an output voltage... |
| US-6,492,863 |
Internal high voltage generation circuit capable of stably generating
internal high voltage and circuit element... In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing... |
| US-6,492,862 |
Charge pump type voltage conversion circuit having small ripple voltage
components A charge pump type voltage conversion circuit comprises a voltage detector which detects whether a boosted output voltage is larger or smaller than a ... |
| US-6,492,861 |
Electronic charge pump device The charge pump device includes, in a cascade arrangement, a plurality of stages (1 to N) for transferring a potential charge from one stage to the next in... |
| US-6,492,860 |
Low voltage CMOS analog switch A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel... |
| US-6,492,859 |
Adjustable electrostatic discharge protection clamp In an ESD protection circuit for an analog bipolar circuit, the avalanche breakdown voltage of a reverse-coupled NPN BJT acting as an avalanche diode is adjusted... |
| US-6,492,858 |
Semiconductor integrated circuit and method for generating a control signal
therefor A semiconductor integrated circuit having a selector 1, which selects either an inverted signal 2B or a non-inverted signal 2A, based on the condition of a read... |
| US-6,492,857 |
Method and apparatus for reducing the vulnerability of latches to single
event upsets A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network... |
| US-6,492,856 |
Edge triggered latch with symmetrical paths from clock to data outputs A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a... |
| US-6,492,855 |
Flip flop which has complementary, symmetric, minimal timing skew outputs The complementary outputs of a master slave flip flop are made symmetric, with substantially zero timing skew over all process, voltage and temperature... |
| US-6,492,854 |
Power efficient and high performance flip-flop A power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip-flop. When the power switch is activated, causing... |
| US-6,492,853 |
Master/slave method for a ZQ-circuitry in multiple die devices An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a... |
| US-6,492,852 |
Pre-divider architecture for low power in a digital delay locked loop A delay locked loop circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain circuit responsive to a clock input... |
| US-6,492,851 |
Digital phase control circuit The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a... |
| US-6,492,850 |
Semiconductor integrated circuit and method for generating internal supply
voltage in semiconductor integrated... The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit... |
| US-6,492,849 |
Supply voltage detection circuit A monitor circuit for supplying a detection voltage reflecting a supply voltage, a reference voltage generation circuit for generating a high-precision reference... |
| US-6,492,848 |
Power-on reset circuit generating reset signal for different power-on
signals The present invention relates to a semiconductor device; and, more particularly, to a power-on reset circuit to produce a stable reset signal irrespective of... |
| US-6,492,847 |
Digital driver circuit A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio... |
| US-6,492,846 |
Semiconductor integrated circuit with input/output interface adapted for
small-amplitude operation A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an... |
| US-6,492,845 |
Low voltage current sense amplifier circuit A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current... |
| US-6,492,844 |
Single-ended sense amplifier with sample-and-hold reference A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal;... |
| US-6,492,843 |
Random frequency clock generator What is disclosed is a system and method of generating a random frequency. First a fundamental noise signal from a fundamental noise source is detected. Then the... |
| US-6,492,842 |
Logic circuit The invention provides a logic circuit which has a sufficient load driving capacity even in its operation with a low power supply voltage and can operate at a... |
| US-6,492,841 |
Integrated NAND and flip-flop circuit A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output... |
| US-6,492,840 |
Current mode logic gates for low-voltage high-speed applications A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The... |
| US-6,492,839 |
Low power dynamic logic circuit A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block,... |
| US-6,492,838 |
System and method for improving performance of dynamic circuits In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body.... |
| US-6,492,837 |
Domino logic with output predischarge A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the... |
| US-6,492,836 |
Receiver immune to slope-reversal noise A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage... |
| US-6,492,835 |
Power saving methods for programmable logic arrays The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA... |
| US-6,492,834 |
Programmable logic device with highly routable interconnect A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs),... |
| US-6,492,833 |
Configurable memory design for masked programmable logic A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and... |
| US-6,492,832 |
Methods for testing a group of semiconductor devices simultaneously, and
devices amenable to such methods of... Methods are provided for testing many semiconductor devices simultaneously. The devices are connected in a group, and checked for DC-type defects. Those... |
| US-6,492,831 |
Current measuring method and current measuring apparatus A current measuring method, which measures a device current flowing through a terminal of a semiconductor device including charging the capacitor which is... |
| US-6,492,830 |
Method and circuit for measuring charge dump of an individual transistor in
an SOI device According to the invention, a method and circuit for measuring a transient of a MOFSET device under measurement of an SOI is provided. The device under... |
| US-6,492,829 |
Contactor for inspection An inspection contactor is provided for inspecting electrical continuity of an inspected wafer by pushing probes against a predetermined location of the... |
| US-6,492,828 |
System and method for detecting bonding status of bonding wire of
semiconductor package The present invention provides schemes which are associated with wire bonding process or wire bonding machine to detect the bonding status of a bonding wire of a... |
| US-6,492,827 |
Non-invasive electrical measurement of semiconductor wafers A semiconductor wafer probe assembly (10) includes a chuck assembly (18, 20) configured to receive a back surface (30) of a semiconductor wafer (14) and an... |
| US-6,492,826 |
Conductive bump array contactors having an ejector and methods of testing
using same The present invention is directed toward conductive bump array contactors having an ejector and methods for testing bumped devices using such apparatus. In one... |
| US-6,492,825 |
Socket and printed circuit board for semiconductor device, and method of
testing semiconductor device A socket and a printed circuit board for testing a semiconductor device packaged by a chip scaled package (CSP) method, and a semiconductor device testing method... |
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