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| Patent # | Description |
|---|---|
| US-6,493,878 |
Method and apparatus for tv broadcasting and reception A television broadcasting system and method of using same for transmitting a plurality of television channel signals is provided. The system includes compression... |
| US-6,493,877 |
Digital data distribution system having a reduced end station memory
requirement A digital data distribution system that comprises a broadcasting station and an end station. The broadcasting station broadcasts a broadcast signal repetitively... |
| US-6,493,876 |
System and method for providing a full service television system A system and method are provided for providing a full service cable television system. The cable system incorporates a digital and analog transmission... |
| US-6,493,875 |
In-home wireless In a residential environment with more than one analog television set a residential gateway has a network interface module which receives signals from a... |
| US-6,493,874 |
Set-top electronics and network interface unit arrangement A set-top electronics and network interface unit arrangement is connected to an internal digital network interconnecting devices in the home. The digital network... |
| US-6,493,873 |
Transmodulator with dynamically selectable channels A system for redistributing a broadband audio-visual-data signal to a multiplicity of receiver units within a multiple dwelling unit (MDU) includes a main... |
| US-6,493,872 |
Method and apparatus for synchronous presentation of video and audio
transmissions and their interactive... A system for synchronizing data streams meant to be displayed concurrently at an end station, but delivered by separate delivery networks is disclosed. In one... |
| US-6,493,871 |
Method and system for downloading updates for software installation A method and system for downloading software update data for installing a revised software product on a client computer minimizes the amount of update data to be... |
| US-6,493,870 |
Methods and apparatus for packaging a program for remote execution A task executing at a server receives a request to package program code for remote execution on a client, and determines the software components that already... |
| US-6,493,869 |
Inheriting code in a transformational programming system A transformation programming system allows code to be inherited. A question and answer methodology is used among question handlers corresponding to nodes of a... |
| US-6,493,868 |
Integrated development tool An integrated code development tool, comprising of an editor, a project management and build system, a debugger, a profiler, and a graphical data visualization... |
| US-6,493,867 |
Digital photolithography system for making smooth diagonal components A digital photolithography system is provided that is capable of making smooth diagonal components. The system includes a computer for providing a first digital... |
| US-6,493,866 |
Phase-shift lithography mapping and apparatus For phase-shifting microlithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes... |
| US-6,493,865 |
Method of producing masks for fabricating semiconductor structures Masks are produced for the fabrication of semiconductor structures based on layout data that has information for defining a mask layout with individual geometric... |
| US-6,493,864 |
Integrated circuit block model representation hierarchical handling of
timing exceptions In a block model abstraction of an integrated circuit developed from a hierarchal netlist, the hierarchal handling of timing exceptions is accomplished by... |
| US-6,493,863 |
Method of designing semiconductor integrated circuit After a program is inputted in the high-level synthesis of system design, blocks each for implementing at least one function and an HW resource connection graph... |
| US-6,493,862 |
Method for compressing an FPGA bitsream An FPGA architecture and method to reduce the size of the bitstream used in configuring or reconfiguring the FPGA. To facilitate features of the compression... |
| US-6,493,861 |
Interconnected series of plated through hole vias and method of fabrication
therefor A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH... |
| US-6,493,860 |
Method of designing semiconductor device, and method of manufacturing
semiconductor device Methods of designing and manufacturing a semiconductor device are disclosed in order to reduce the manufacturing cost of the semiconductor device, and to easily... |
| US-6,493,859 |
Method of wiring power service terminals to a power network in a
semiconductor integrated circuit Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power... |
| US-6,493,858 |
Method and system for displaying VLSI layout data A VLSI layout editor and method for using same that increases display and re-display speed and accuracy uses properties inherent to VLSI layouts that allows them... |
| US-6,493,857 |
Matching circuit parts between circuitry-related documents A device for matching information between a plurality of circuitry-related documents includes a tree generation unit which generates a tree that represents... |
| US-6,493,856 |
Automatic circuit generation apparatus and method, and computer program
product for executing the method An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an... |
| US-6,493,855 |
Flexible cache architecture using modular arrays A system and method which implement a memory component of an integrated circuit as multiple, relatively small sub-arrays of memory to enable great flexibility in... |
| US-6,493,854 |
Method and apparatus for placing repeaters in a network of an integrated
circuit A method of inserting repeaters into a network to improve timing characteristics of the network. Extraction and timing tools provide an RC network description... |
| US-6,493,853 |
Cell-based noise characterization and evaluation In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on... |
| US-6,493,852 |
Modeling and verifying the intended flow of logical signals in a hardware
design A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of... |
| US-6,493,851 |
Method and apparatus for indentifying causes of poor silicon-to-simulation
correlation A method identifies the cause of poor correlation between an integrated circuit model and measured integrated circuit performance. The method includes... |
| US-6,493,850 |
Integrated circuit design error detector for electrostatic discharge and
latch-up applications For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is... |
| US-6,493,849 |
Method for determining the steady state behavior of a circuit using an
iterative technique An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a... |
| US-6,493,848 |
Rate equation method and apparatus for simulation of current in a MOS
device An improved method for modeling electrical behavior in a MOSFET semiconductor device is disclosed wherein a rate equation qualitatively predicts electrical... |
| US-6,493,847 |
Sonet B2 parity byte calculation method and apparatus The invention is directed to a technique for recalculating a bit interleave parity (BIP) byte for byte interleaved SONET/SDH frames. An interleaved SONET/SDH... |
| US-6,493,846 |
Signal processing apparatus and method, and data recording/reproducing
apparatus using the same A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing... |
| US-6,493,845 |
Parallel input output combined system for producing error correction code
redundancy symbols and error syndromes A parallel input/output combined encoding and syndrome generating system encodes two information symbols per clock cycle, and thereafter, produces two redundancy... |
| US-6,493,844 |
Error detector, semiconductor device, and error detection method An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a... |
| US-6,493,843 |
Chipkill for a low end server or workstation The present invention provides a process and memory configuration for providing chipkill error detection in a low end server without requiring non-standard... |
| US-6,493,842 |
Time-varying randomization for data synchronization and implicit
information transmission The present invention provides a system and method for the time-varying randomization of a signal stream to provide for a robust error recovery. A current block... |
| US-6,493,841 |
Method and apparatus for determining expected values during circuit design
verification Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by... |
| US-6,493,840 |
Testability architecture for modularized integrated circuits A testability architecture and method for loosely integrated (modularized) integrated circuits uses stand alone module testing. For an integrated circuit chip... |
| US-6,493,839 |
Apparatus and method for testing memory in a microprocessor An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic... |
| US-6,493,838 |
Coding apparatus and decoding apparatus for transmission/storage of
information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check... |
| US-6,493,837 |
Using log buffers to trace an event in a computer system An event tracing program generally receives performance data about an event occurring on the computer system from a data producer program. The event tracing... |
| US-6,493,836 |
Method and apparatus for scheduling and using memory calibrations to reduce
memory errors in high speed memory... A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or... |
| US-6,493,835 |
System and method for detecting media and transport degradation during
multichannel recording A method and system for determining degradation of the tape drive and the tape in a multichannel recording system provides refined definition of correction for... |
| US-6,493,834 |
Apparatus and method for dynamically defining exception handlers in a
debugger An apparatus and method allow dynamically defining exception handlers in a debugger and breaking only when one of the dynamically-defined exception handlers is... |
| US-6,493,833 |
Microcomputer A microcomputer including a built-in storage portion capable of executing an evaluation program by an ICE through a simple operation also when the evaluation... |
| US-6,493,832 |
Communication apparatus which handles a time stamp A transmission side of a communication apparatus of the present invention makes use of a clock signal synchronized with a network to transmit an arrival interval... |
| US-6,493,831 |
Timer circuits for a microcomputer A select circuit selectively outputs one of a transition indication signal that is the output of an edge sense circuit of an input timer, a transition indication... |
| US-6,493,830 |
Clock control device used in image formation Video data (default data in case of a black original) output from a CCD line sensor 405 upon reading an image while a light source is kept OFF corresponds to... |
| US-6,493,829 |
Semiconductor device enable to output a counter value of an internal clock
generation in a test mode In a SDRAM, a switch circuit is provided between a memory circuit and a data output circuit. The switch circuit provides data read out from the memory circuit to... |
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