Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-6,515,916 |
Column switch in memory device and cache memory using the same A cache memory is provided with a tag memory for storing tag information and a column switch having an XOR calculation function, XOR calculation for judging... |
| US-6,515,915 |
Circuits and methods for outputting multi-level data through a single
input/output pin A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional... |
| US-6,515,914 |
Memory device and method having data path with multiple prefetch I/O
configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into... |
| US-6,515,913 |
Semiconductor memory device and defect remedying method thereof Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal... |
| US-6,515,912 |
Semiconductor device A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (T.sub.WR) a read transistor (T.sub.RE), a sense... |
| US-6,515,911 |
Circuit structure for providing a hierarchical decoding in semiconductor
memory devices A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory... |
| US-6,515,910 |
Bit-by-bit Vt-correction operation for nonvolatile semiconductor
one-transistor cell, nor-type flash EEPROM A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under... |
| US-6,515,909 |
Flash memory device with a variable erase pulse A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to... |
| US-6,515,908 |
Nonvolatile semiconductor memory device having reduced erase time and
method of erasing data of the same Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be... |
| US-6,515,907 |
Complementary non-volatile memory circuit A non-volatile memory circuit has FLOTOX type memory elements operable with a low data writing voltage even when a difference between threshold voltages of... |
| US-6,515,906 |
Method and apparatus for matched-reference sensing architecture for
non-volatile memories According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a... |
| US-6,515,905 |
Nonvolatile semiconductor memory device having testing capabilities Included are a memory cell array 10, a sense amplifier 21 for determining a cell storage value by comparing a signal value read out from an addressed EEPROM cell... |
| US-6,515,904 |
Method and system for increasing programming bandwidth in a non-volatile
memory device The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred... |
| US-6,515,903 |
Negative pump regulator using MOS capacitor A system is disclosed for generating a regulated negative charge pump voltage for flash memory operations, wherein a capacitive voltage divider circuit... |
| US-6,515,902 |
Method and apparatus for boosting bitlines for low VCC read A memory device is disclosed having a memory cell in electrical communication with a node, and operative to indicate a binary value associated with data stored... |
| US-6,515,901 |
Method and apparatus for allowing continuous application of high voltage to
a flash memory device power pin According to one aspect of the present invention, an apparatus is provided in which a first switching device is used to connect a first node to a second node and... |
| US-6,515,900 |
Non-volatile memory with background operation function A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to... |
| US-6,515,899 |
Non-volatile memory cell with enhanced cell drive current A non-volatile memory cell is disclosed with increased drive current. A low voltage read transistor is used to increase the drive current. However, with a low... |
| US-6,515,898 |
Memory element, method for structuring a surface, and storage device The invention is essentially characterized in that in a first step a substrate is provided, which is coated with defined pattern of protrusions of a coating... |
| US-6,515,897 |
Magnetic random access memory using a non-linear memory element select
mechanism A non-volatile memory array having a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically... |
| US-6,515,896 |
Memory device with short read time The memory device includes a memory array of memory cells, and intersecting word lines and bit lines. At one end of the array, a bank of read/write select... |
| US-6,515,895 |
Non-volatile magnetic register A non-volatile, bistable magnetic tunnel junction (MTJ) register cell includes first and second magnetic tunnel junctions connected for differential operation.... |
| US-6,515,894 |
Semiconductor memory apparatus, semiconductor apparatus, data processing
apparatus and computer system A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a... |
| US-6,515,893 |
Source pulsed, low voltage CMOS SRAM cell for fast, stable operation A source pulsed complementary metal oxide semiconductor static random access memory offers higher cell stability, lower bit line delay, and lower standby power... |
| US-6,515,892 |
Semiconductor integrated circuit device A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information... |
| US-6,515,891 |
Random access memory with hidden bits A random access memory having a multiplicity of memory cells having logic states that can be changed by a control voltage. At least some of the memory cells... |
| US-6,515,890 |
Integrated semiconductor memory having memory cells with a ferroelectric
memory property An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a... |
| US-6,515,889 |
Junction-isolated depletion mode ferroelectric memory Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between... |
| US-6,515,888 |
Low cost three-dimensional memory array A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small ... |
| US-6,515,887 |
Semiconductor memory device A semiconductor memory device according to the present invention comprises a memory cell array divided into a plurality of sub-arrays in each of which a... |
| US-6,515,886 |
Electronic apparatus having socket incorporating switch operated by
insertion of electronic circuit device In an electronic apparatus including an electronic circuit device, a board and a control circuit device for controlling the electronic circuit device, a socket... |
| US-6,515,885 |
Tri-stating address input circuit An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one... |
| US-6,515,884 |
Content addressable memory having reduced current consumption According to one embodiment, a content addressable memory (CAM) can include at least one match line (404), series-coupled transistor pairs comprising match... |
| US-6,515,883 |
Single-stage power converter and an uninterruptible power supply using same Presented is a single-stage power converter topology allowing for power factor correction during operation. The topology utilizes an integration of Cuk converter... |
| US-6,515,882 |
Power supply apparatus for lamp A power supply apparatus useful for starting and driving a discharge lamp 22 includes a DC-to-DC converter 16 for converting a DC signal from a DC power supply... |
| US-6,515,881 |
Inverter operably controlled to reduce electromagnetic interference A lamp load control system that includes a lamp controller comprising an inverter generating an AC signal from a DC signal, a load coupled to the inverter, and a... |
| US-6,515,880 |
Soft-start control for DC/DC switching regulators Startup operation of a DC/DC switching regulator is controlled by providing a first signal (MAXDC) whose waveform has a duty cycle that varies over time,... |
| US-6,515,879 |
Power source filter circuit that is capable of eliminating noise component
supplied from power source and... The power source filter circuit is provided with a first inductor and a second inductor connected in series between an input terminal and an output terminal, a... |
| US-6,515,878 |
Method and apparatus for supplying contactless power A method and apparatus for supplying contactless power. Electrical power is transferred from a power source to a load through a primary energy converter that can... |
| US-6,515,877 |
DC-to-DC converter providing high current and low voltage Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter includes: a synchronous rectifier converter. The synchronous rectifier... |
| US-6,515,876 |
Dc-to-dc converter A transformer has a primary winding connected between a pair of d.c. input terminals via an on-off switch, and a secondary winding connected between a pair of... |
| US-6,515,875 |
Switching power supply circuit A power supply circuit has a so-called composite resonance type switching converter equipped with a primary resonance circuit for forming a voltage resonance... |
| US-6,515,874 |
Clocked power supply The integrable control circuit drives a semiconductor switch in a switched-mode power supply. The control circuit has a control unit for producing control pulses... |
| US-6,515,873 |
Switched-mode power supply A switched-mode power supply has a storage capacitor, a transformer with a primary winding and at least one secondary winding, and also a switching transistor... |
| US-6,515,872 |
Automobile and electric power system controller thereof This electric power system controller for an automobile secures satisfactory driving control of a vehicle and outputs 100 V AC using electric power from a... |
| US-6,515,871 |
Protection shield for an electronic cartridge A shield for an electronic cartridge which has a pin that attaches a thermal element to a substrate. One edge of the substrate may have a plurality of conductive... |
| US-6,515,870 |
Package integrated faraday cage to reduce electromagnetic emissions from an
integrated circuit An integrated circuit (IC) includes a package-integrated Faraday cage assembly to reduce the level of electromagnetic radiation emanating from the IC during... |
| US-6,515,869 |
Supporting substrate for a semiconductor bare chip A supporting substrate for mounting a semiconductor bare chip thereon has a surface provided with electrode pads thereon and bumps on the electrode pads. A... |
| US-6,515,868 |
Printed circuit board Printed circuit board 1 on which LSI2 is mounted comprises first capacitors 4a and 4b for electrically connecting power source terminals 3a and 3b to via holes... |
| US-6,515,867 |
Screw-less fixing structure A screw-less fixing structure is provided for users to mount the add-on card onto a PC. The screw-less fixing structure comprises a support plate, a rotational... |
Copyright 2008−2012 Patents.com
