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| Patent # | Description |
|---|---|
| US-6,516,418 |
Portable computer having universal serial bus ports controlled power supply
and a method of the same A portable computer system with universal serial bus (USB) port or ports and a method for controlling power of the universal serial bus (USB) port is described.... |
| US-6,516,417 |
Virtual private networks A system and method of automatically configuring virtual private networks is provided. The virtual private networks disclosed, include multiple routers... |
| US-6,516,416 |
Subscription access system for use with an untrusted network A system and method is disclosed for controlling access to computer resources using an untrusted network. The system preferably uses a hardware key connected to... |
| US-6,516,415 |
Device and method of maintaining a secret code within an integrated circuit
package A device and method for safely maintaining a secret code within an integrated circuit (IC) package. The complete secret code is divided into two parts. The first... |
| US-6,516,414 |
Secure communication over a link A method and apparatus of protecting communications in a receiver having a first and a second module includes issuing a request to a transmitter. The identities... |
| US-6,516,413 |
Apparatus and method for user authentication An apparatus and method for user authentication for easily realizing the allocation of a complexity of rights when controlling access by a plurality of users to... |
| US-6,516,412 |
Authorization of services in a conditional access system A cable television system provides conditional access to services. The cable television system includes a headend from which service "instances", or programs,... |
| US-6,516,411 |
Method and apparatus for effecting secure document format conversion A method and apparatus is provided for effecting secure document delivery in any of various document formats. A document is encrypted with the public key of a... |
| US-6,516,410 |
Method and apparatus for manipulation of MMX registers for use during
computer boot-up procedures A system for execution of code during power-on-self test (POST), the system including a mass storage device for storing computer programs; a microprocessor... |
| US-6,516,409 |
Processor provided with a data value prediction circuit and a branch
prediction circuit A processor includes at least one functional unit configured to execute an instruction. The processor also includes an instruction window configured to supply... |
| US-6,516,408 |
Various length software breakpoint in a delay slot A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy... |
| US-6,516,407 |
Information processor To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition... |
| US-6,516,406 |
Processor executing unpack instruction to interleave data elements from two
packed data An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source... |
| US-6,516,405 |
Method and system for safe data dependency collapsing based on control-flow
speculation The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because... |
| US-6,516,404 |
Data processing system having hashed architected processor facilities A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and... |
| US-6,516,403 |
System for synchronizing use of critical sections by multiple processors
using the corresponding flag bits in... A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality... |
| US-6,516,402 |
Information processing apparatus with parallel accumulation capability An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and... |
| US-6,516,401 |
Data reading method and data reading apparatus The present invention provides, at a lower cost, a highly reliable data reading method and data reading apparatus that can improve backward sequential reading... |
| US-6,516,400 |
Data storage, data processing system and method When reading or writing data from or to a flash memory, a table indicating the correspondence between physical addresses of physical blocks composing together a... |
| US-6,516,399 |
Dynamically configurable page table The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and... |
| US-6,516,398 |
Program-downloadable data processing system and method for accessing memory
by using a unified memory space therein A data processing system and a method for accessing data therein. The data processing system includes a microprocessor, an application specific integrated... |
| US-6,516,397 |
Virtual memory system utilizing data compression implemented through a
device A method of operating a data processing system having a main memory divided into memory pages that are swapped into and out of main memory when the main memory... |
| US-6,516,396 |
Means to extend tTR range of RDRAMS via the RDRAM memory controller A method and system for extending t.sub.TR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group... |
| US-6,516,395 |
System and method for controlling access to a privilege-partitioned address
space with a fixed set of attributes A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a... |
| US-6,516,394 |
System and method for management of storage devices using labels This invention is a data storage system that includes logic configured for carrying out a method to allow a so-called "re-labeling" of a logical volume.... |
| US-6,516,393 |
Dynamic serialization of memory access in a multi-processor system A method for resolving address contention and prioritization of access to resources within a shared memory system includes dynamically creating ordered lists of... |
| US-6,516,392 |
Address and data transfer circuit An address and data transfer circuit includes enable circuit for enabling a single-port memory in accordance with an access requirement from a corresponding port... |
| US-6,516,391 |
Multiprocessor system and methods for transmitting memory access
transactions for the same In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled... |
| US-6,516,390 |
Methods and apparatus for accessing data within a data storage system The invention is directed to techniques for accessing data within a data storage system having a circuit board that includes both a front-end circuit for... |
| US-6,516,389 |
Disk control device A pre-fetch prediction table is provided for storing history of readout access given from a host device. A controller in a disk control device registers entry... |
| US-6,516,388 |
Method and apparatus for reducing cache pollution In a cache which writes new data over less recently used data, methods and apparatus which dispense with the convention of marking new cache data as most... |
| US-6,516,387 |
Set-associative cache having a configurable split and unified mode A set-associative cache having a selectively configurable split/unified mode. The cache may comprise a memory and control logic. The memory may be configured for... |
| US-6,516,386 |
Method and apparatus for indexing a cache A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the... |
| US-6,516,385 |
Data sharing method and system between information processing systems with
variable length block format to... A data sharing method and system between information processing systems which enable an information processing system to share data in an internal disk unit... |
| US-6,516,384 |
Method and apparatus to perform a round robin and locking cache replacement
scheme A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers... |
| US-6,516,383 |
Techniques for efficient location of free entries for TCAM inserts Techniques for the efficient location of free entries for use in performing insert operations in a binary or ternary content addressable memory. As used in data... |
| US-6,516,382 |
Memory device balanced switching circuit and method of controlling an array
of transfer gates for fast... A memory device including a balanced switching circuit and methods for controlling an array of transfer gates. The balanced switching circuit comprises a... |
| US-6,516,381 |
Supplying voltage to a memory module Included in the system are a memory module, a controller, and a voltage regulator. The memory module stores data indicating a level of voltage needed for... |
| US-6,516,380 |
System and method for a log-based non-volatile write cache in a storage
controller A computer-implemented method and system for accelerating writes to a storage controller by performing log-based sequential write caching of data to be written... |
| US-6,516,379 |
Method and apparatus for transaction pacing to reduce destructive
interference between successive transactions... A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system... |
| US-6,516,378 |
Microprocessor for controlling busses The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are... |
| US-6,516,377 |
Self-configuring modular electronic system In an electronic system, an arithmetic device is provided between successive bus terminals or between successive modules, respectively, with an identification... |
| US-6,516,376 |
Command and control architecture for a video decoder and a host A method and apparatus for using an interface and concomitant communication protocol to allow a host to control and communicate with a video decoder. More... |
| US-6,516,375 |
Peripheral component interconnect (PCI) configuration emulation for hub
interface A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address... |
| US-6,516,374 |
Method for docking/undocking a portable computer to/from an expansion unit A method for docking/undocking a portable computer to/from an expansion unit is disclosed. The portable computer includes a main battery, and the expansion unit... |
| US-6,516,373 |
Common motherboard interface for processor modules of multiple
architectures A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a... |
| US-6,516,372 |
Partitioning a distributed shared memory multiprocessor computer to
facilitate selective hardware maintenance A distributed shared memory multiprocessor computer system is provided, which has a number of processors and is divided into partitions. Each partition has... |
| US-6,516,371 |
Network interface device for accessing data stored in buffer memory
locations defined by programmable read... A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer... |
| US-6,516,370 |
Data storage system A system for coupling data between a host computer and a bank of disk drives. The system includes a plurality of directors for controlling the flow of the data... |
| US-6,516,369 |
Fair and high speed arbitration system based on rotative and weighted
priority monitoring A mixed rotative and weighted arbiter for arbitrating the priority of request signals R1-Rn supplied from a plurality of devices is disclosed. The arbiter is... |
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