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| Patent # | Description |
|---|---|
| US-6,523,128 |
Controlling power for a sleeping state of a computer to prevent overloading
of the stand-by power rails by... A computer receives a sleep signal that instructs the computer to enter a sleeping state in which stand-by power from a power source is needed. The computer... |
| US-6,523,127 |
Display apparatus having a power saving mode A display apparatus connected to a personal computer for carrying out character display or graphic display in accordance with information from the personal... |
| US-6,523,126 |
Watchdog timer that is disabled upon receiving sleep status signal from
monitored device wherein monitored... A system comprises a first device and a second device. The first device operates in a power management environment and has a sleep status signal for indicating a... |
| US-6,523,125 |
System and method for providing a hibernation mode in an information
handling system To provide an information handling system and a method of controlling the same which allows the state of the system to be saved without destructing other user... |
| US-6,523,124 |
System and method for detection of an accessory device connection status Embodiments of this invention provide for a portable computer that determines whether an accessory device is actively connected to it. In one embodiment, the... |
| US-6,523,123 |
Method and apparatus for providing intelligent power management The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a... |
| US-6,523,122 |
Computer system for displaying system state information including advanced
configuration and power interface... A computer system has a display device for displaying system state information, so that advanced configuration and power interface specification (ACPI) state... |
| US-6,523,121 |
Bus system with a reduced number of lines In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a... |
| US-6,523,120 |
Level-based network access restriction Methods and apparatuses for level-based network access restriction are described. A user of network resources logs on to the network according to any appropriate... |
| US-6,523,119 |
Software protection device and method A method and apparatus for protecting computer software from unauthorized execution or duplication using a hardware key is disclosed. The apparatus comprises a... |
| US-6,523,118 |
Secure cache for instruction and data protection A computing system, includes a processor, a cache, a memory system, and a secure cache controller system. The cache stores a plurality of cache lines. The memory... |
| US-6,523,117 |
System and method of online deciphering data on storage medium The user mounts a distributed storage medium in his or her terminal unit, selects desired information from stored information, and notifies the host central... |
| US-6,523,116 |
Secure personal information card database system A database system for personal information includes storing personal information in a database remote from the person using the public key of a person as a... |
| US-6,523,115 |
ENCRYPTION DEVICE, DECRYPTION DEVICE, ENCRYPTION METHOD, DECRYPTION METHOD,
CRYPTOGRAPHY SYSTEM,... In a cryptography system, plaintext storage unit 101 stores a plaintext. Encryption unit 102 encrypts the plaintext to generate a ciphertext. First verification... |
| US-6,523,114 |
Method and apparatus for embedding authentication information within
digital data Arbitrary digital information is embedded within a stream of digital data, in a way that avoids detection by a casual observer and that allows a user to... |
| US-6,523,113 |
Method and apparatus for copy protection Copy protection techniques that utilize a watermark and a permission key are disclosed. The copy protection techniques can provide single-copy copy protection in... |
| US-6,523,112 |
Operating system software boot program execution method A data server having a plurality of hot replaceable processing unit modules. Each module includes a motherboard having plugged therein: a CPU; a main memory; an... |
| US-6,523,111 |
Remote configuration/setup of computer systems operated as embedded
controllers without keyboard or video... Method and program product operable on a computer for changing configuration/setup parameters in an embedded controller type X86 based computer system, the... |
| US-6,523,110 |
Decoupled fetch-execute engine with static branch prediction support There is provided a decoupled fetch-execute engine with static branch prediction support. A method for prefetching targets of branch instructions in a computer... |
| US-6,523,109 |
Store queue multimatch detection A processor includes a store queue configured to detect a hit on a store queue entry for a load being executed by the processor, and to forward data from the... |
| US-6,523,108 |
Method of and apparatus for extracting a string of bits from a binary bit
string and depositing a string of... Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the... |
| US-6,523,107 |
Method and apparatus for providing instruction streams to a processing
device A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other... |
| US-6,523,106 |
Method and apparatus for efficient pipelining Only one pipe in superscalar microprocessor contains particular functional logic necessary to process a specific instruction. When the specific instruction... |
| US-6,523,105 |
Recording medium control device and method An information recording/reproducing device includes a transfer control section for carrying out input/output of transfer data, a recording medium control... |
| US-6,523,104 |
Mechanism for programmable modification of memory mapping granularity An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit... |
| US-6,523,103 |
Disablement of a write filter stored on a write-protected partition A computer system having at least primary and secondary partitions, a primary write filter for write-protecting the primary partition, and a state machine. The... |
| US-6,523,102 |
PARALLEL COMPRESSION/DECOMPRESSION SYSTEM AND METHOD FOR IMPLEMENTATION OF
IN-MEMORY COMPRESSED CACHE IMPROVING... An ASIC device embedded into the memory subsystem of a computing device used to accelerate the transfer of active memory pages for usage by the system CPU from... |
| US-6,523,101 |
Installed-software development assistance system In order to appropriately assign a plurality of programs to a plurality of storage devices, a header file and a source file are compiled by a compiling... |
| US-6,523,100 |
Multiple mode memory module A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an... |
| US-6,523,099 |
Integrated circuit with output inhibit feature and a control port to
receive an inhibit release password In an integrated circuit in which data can be read out from a memory (107) by supplying control data through an access port (101), this integrated circuit... |
| US-6,523,098 |
Mechanism for efficient low priority write draining In one embodiment, a method and apparatus for servicing a request for an opportunistic operation to a memory subsystem includes an enabling signal that is... |
| US-6,523,097 |
Unvalue-tagged memory without additional bits There is provided a method for representing unvalues in an unvalue-unaware memory of a computer processing system. The method includes the step of selecting... |
| US-6,523,096 |
Apparatus for and method of accessing a storage region across a network N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of... |
| US-6,523,095 |
Method and data processing system for using quick decode instructions A cache line of a cache (230) contains a modifiable instruction. The modifiable instruction is decoded by a central processor unit (210) (CPU) which performs the... |
| US-6,523,094 |
Portable information processing terminal device with low power consumption
and large memory capacity A portable information processing terminal device, realizing both a low power consumption and a large memory capacity, is formed by a first memory for storing... |
| US-6,523,093 |
Prefetch buffer allocation and filtering system A system is described for prefetching data from a main memory before the data is requested by a processor. The system includes a prefetch buffer having a number... |
| US-6,523,092 |
Cache line replacement policy enhancement to avoid memory page thrashing A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request... |
| US-6,523,091 |
Multiple variable cache replacement policy A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes... |
| US-6,523,090 |
Shared instruction cache for multiple processors The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared... |
| US-6,523,089 |
Memory controller with power management logic A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that... |
| US-6,523,088 |
Disk array controller with connection path formed on connection request
queue basis A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for... |
| US-6,523,087 |
Utilizing parity caching and parity logging while closing the RAID5 write
hole A method for enhancing the performance on non-full stripe writes while closing the RAID5 write hole is disclosed. When a RAID controller receives data to be... |
| US-6,523,086 |
Method for improving performance of read cache of magnetic disk drive A method for improving the performance of a read cache of a magnetic disk drive includes: a data transmission process for reading corresponding data from the... |
| US-6,523,085 |
Disk drive and method of multi-block size addressing A disk drive that is enabled by information contained in a mode page and in a command to access data blocks of either a small size (e.g., 512 bytes) or of a... |
| US-6,523,084 |
Data processing apparatus To provide a data processing apparatus that allows the occurrence of a gate disturb effect to be reduced and the reliability of data processing using the... |
| US-6,523,083 |
System and method for updating flash memory of peripheral device A system for updating a flash memory of a peripheral device including a host sending an update content. The host sends an update content. The peripheral device... |
| US-6,523,082 |
Systems having shared memory and buses In a system having a plurality of CPUs connected to a plurality of corresponding bus bridges which are connected in tandem, one of the plurality of bus bridges... |
| US-6,523,081 |
Architecture using dedicated endpoints and protocol for creating a
multi-application interface and improving... A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host,... |
| US-6,523,080 |
Shared bus non-sequential data ordering method and apparatus A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum... |
| US-6,523,079 |
Micropersonal digital assistant A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector... |
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