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| Patent # | Description |
|---|---|
| US-6,614,705 |
Dynamic random access memory boosted voltage supply A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a... |
| US-6,614,704 |
Circuit and method for refreshing memory cells in a DRAM The memory cells of a DRAM are refreshed such that the temporal sequence of the control signals for triggering the information refresh operation for the... |
| US-6,614,703 |
Method and system for configuring integrated systems on a chip A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method... |
| US-6,614,702 |
Semiconductor memory devices and methods including coupling and/or floating
isolation control signal lines A semiconductor memory device may include a memory cell array comprising a plurality of memory cells, a pair of bit lines coupled to at least one memory cell of... |
| US-6,614,701 |
Weak bit testing Apparatus for testing an integrated circuit, the integrated circuit comprising a plurality of semiconductor memory cells connected by a common word-line, each... |
| US-6,614,700 |
Circuit configuration with a memory array The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal... |
| US-6,614,699 |
Booster circuit for raising voltage by sequentially transferring charges
from input terminals of booster units... A booster circuit includes a plurality of booster units whose output terminals are respectively connected to the input terminals of the next-stage booster units,... |
| US-6,614,698 |
Method and apparatus for synchronous data transfers in a memory device with
selectable data or address paths A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM... |
| US-6,614,697 |
Diode-based multiplexer A multiplexer includes a plurality of stages. Each stage includes a storage device coupled to a data output; a first diode coupled between a data input and a... |
| US-6,614,696 |
Semiconductor device having memory cells coupled to read and write data
lines A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the... |
| US-6,614,695 |
Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory... |
| US-6,614,694 |
Erase scheme for non-volatile memory A method of an erase scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, source, drain with a channel region and a gate... |
| US-6,614,693 |
Combination erase waveform to reduce oxide trapping centers generation rate
of flash EEPROM A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper... |
| US-6,614,692 |
EEPROM array and method for operation thereof A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory... |
| US-6,614,691 |
Flash memory having separate read and write paths A non-volatile memory device having separate read and write paths. In one embodiment, a flash memory device has a memory array, a first multiplexer and a second... |
| US-6,614,690 |
Non-volatile memory having a control mini-array A flash memory device having a mini array to store operating parameters. In one embodiment, the flash memory device comprises at least one array block of memory,... |
| US-6,614,689 |
Non-volatile memory having a control mini-array A flash memory device having a mini array to store operating parameters. In one embodiment, the flash memory device comprises at least one array block of memory,... |
| US-6,614,688 |
Method of programming non-volatile semiconductor memory device A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step,... |
| US-6,614,687 |
Current source component with process tracking characteristics for compact
programmed Vt distribution of flash... A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which... |
| US-6,614,686 |
Nonvolatile memory circuit for recording multiple bit information The present invention provides a multi-bits non-volatile memory circuit having a cell transistor with non-conductive trap gate which has a cell array capable of... |
| US-6,614,685 |
Flash memory array partitioning architectures A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one... |
| US-6,614,684 |
Semiconductor integrated circuit and nonvolatile memory element An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile... |
| US-6,614,683 |
Ascending staircase read technique for a multilevel cell NAND flash memory
device A method for resolving data to one stored level of N possible stored levels in a multi-level memory includes receiving an access address associated with a memory... |
| US-6,614,682 |
Magnetic material memory and information reproducing method of the same To provide an MRAM, in which the information readout speed of the MRAM is increased up to a speed comparable to a synchronous DRAM, the MRAM includes a plurality... |
| US-6,614,681 |
Thin film magnetic memory device with memory cells including a tunnel
magnetic resistive element A data bus is precharged to a precharge voltage before data read operation. In the data read operation, the data bus thus precharged is electrically coupled to... |
| US-6,614,680 |
Current leakage reduction for loaded bit-lines in on-chip memory structures Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access... |
| US-6,614,679 |
Semiconductor memory device A DRAM is provided that can reduce the time required for completion of a writing operation on a memory cell so as to speed up a random access cycle. The DRAM... |
| US-6,614,678 |
Semiconductor memory and method for driving the same A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another... |
| US-6,614,676 |
Content-addressable memory device A content-addressable memory device with multiple WORD lines has: a first memory block to store whether there is a hit during current time period; a second... |
| US-6,614,675 |
Pipelined content addressable memory with read only element encoding scheme A content addressable memory (CAM) has a CAM array and a CAM encoder. The CAM array in response to data stored in a memory address of the CAM array matching... |
| US-6,614,674 |
Regulator circuit for independent adjustment of pumps in multiple modes of
operation A regulator circuit with at least two independently selectable and adjustable adjustment circuits. Each adjustment circuit may be connected across a standard... |
| US-6,614,672 |
Voltage generator A rectifier circuit 30 of a voltage genetator 100 rectifys a alternating current signals through the use of the electromagnetic induction of a coil 11, the... |
| US-6,614,671 |
Dual isolated power supply inputs A power supply system for providing power from either a first power supply or a second power supply to an ultimate rectified output. The system consists of a... |
| US-6,614,670 |
Isolation circuit for providing isolation from a switch of a welding power
supply A circuit for controlling the welding power of a welding power supply includes a control circuit, a switch, and an isolation circuit. The control circuit is... |
| US-6,614,669 |
Power supply starting system A power supply starting system which is capable of preventing faulty starting from being caused at the time of simultaneous startup and thus is improved in... |
| US-6,614,668 |
Method and system for limiting in rush current of a power supply filter A power supply is filtered while the amount of in-rush current required by the capacitive charging of the filter is limited. A resistor may be placed in parallel... |
| US-6,614,667 |
Method and apparatus for driving switching element in power converter A power conversion apparatus capable of reducing the conduction loss to achieve high efficiency yielding a downsized and weight-reduced apparatus and a method... |
| US-6,614,666 |
Universal output driver A circuit for driving a communication line includes a transformer having a secondary winding for supplying an output drive signal, and having a primary winding... |
| US-6,614,665 |
Cable management bracket for a telecommunications rack A cable management bracket for a telecommunications rack. The bracket includes an elongated member having a length sized to extend across a width of the rack. A... |
| US-6,614,664 |
Memory module having series-connected printed circuit boards A memory module having series-connected printed circuit boards is provided. The memory module comprises a plurality of printed circuit boards, each comprising a... |
| US-6,614,663 |
Reducing impedance of power supplying system in a circuit board by
connecting two points in one of a power... In a circuit board having a multilayer structure comprising a ground pattern and a power-supply pattern both, for example, by forming a plurality of slits along... |
| US-6,614,662 |
Printed circuit board layout A PCSB assembly including a PCSB; a first plurality of LVD SCSI bus signal trace pairs formed in the PCSB; a second plurality of LVD SCSI bus signal trace pairs... |
| US-6,614,661 |
Covering device for ceramic modules The covering device covers a ceramic module with electronic components arranged between a ceramic substrate and an upper covering plate of the covering device.... |
| US-6,614,660 |
Thermally enhanced IC chip package A thermally enhanced IC chip package has a dielectric substrate member with conductive circuit patterns on top and bottom surfaces thereof and an opening... |
| US-6,614,659 |
De-mountable, solderless in-line lead module package with interface Apparatus for holding and securing an electrical module, IC, or other electronic components to a PCB that is easy to use and manipulate. The apparatus utilizes a... |
| US-6,614,658 |
Flexible cable stiffener for an optical transceiver An optical transceiver utilizes a stiffener including a surface adapted for attachment of a portion of a flexible circuit having electrical components that... |
| US-6,614,657 |
Heat sink for cooling an electronic component of a computer The heat sink is described which is used to cool an electronic component of a computer. The heat sink is constructed from a metal sheet which is bent so as to... |
| US-6,614,656 |
Display device with hidden air vents A display device with hidden air vents includes a main body and a casing. The main body includes a heat generating source. The casing is coupled with the main... |
| US-6,614,655 |
Method of controlling cooling system for a personal computer and personal
computer In an information processing apparatus such as a space-saving type personal computer having a liquid-cooling type cooling system, the presence of a cooling... |
| US-6,614,654 |
Fixing apparatus for data storage devices A fixing apparatus for data storage devices (80) includes a drive bracket (20) and a fixing plate (40). The drive bracket includes two side panels (22, 24)... |
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