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| Patent # | Description |
|---|---|
| US-6,615,358 |
Firewall for processing connection-oriented and connectionless datagrams
over a connection-oriented network The present invention is a device for and method of accessing an information network by initializing a database, an ATM approved list, an IP approved list, and... |
| US-6,615,357 |
System and method for network address translation integration with IP
security IP security is provided in a virtual private network using network address translation (NAT) by performing one or a combination-of the three types of VPN NAT,... |
| US-6,615,356 |
System and method for controlling a system power supply using a password In a system such as a computer system, and in a power controlling method for the system, power applied to the overall system is controlled according to... |
| US-6,615,355 |
Method and apparatus for protecting flash memory In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory... |
| US-6,615,354 |
Information processing equipment A relation between the data process contents in an IC card chip and the consumption current of the IC card chip is reduced. Prior to executing an input data... |
| US-6,615,353 |
User authentication method and user authentication system A user authentication method and system which maintains reliable security using a low cost storage medium in place of cryptocards, wherein the system comprises... |
| US-6,615,352 |
Device and method for authenticating user's access rights to resources A burden caused by handling a large number of unique identifying information pieces such as authentication keys is to be lightened from both the user side and... |
| US-6,615,351 |
Method for checking the authenticity of a data medium In a method for checking the authenticity of a data medium, in particular a smart card, the encrypted form of a physical feature of the data medium is stored in... |
| US-6,615,350 |
Module authentication and binding library extensions An apparatus, system, and method to provide an initial and an on-going authentication mechanism with which two executable entities may unilaterally or... |
| US-6,615,349 |
System and method for manipulating a computer file and/or program A system for manipulating a computer file and/or program. The system includes a serving device having access to a computer file and/or program which is... |
| US-6,615,348 |
Method and apparatus for an adapted digital signature A method and apparatus for an authenticated electronic userid comprising an adapted digital signature is provided. According to an aspect of the present... |
| US-6,615,347 |
Digital certificate cross-referencing As part of a security infrastructure based on public-key cryptography, a first digital certificate (200) is issued by a first certification authority (104) to a... |
| US-6,615,346 |
System providing switching means on print setup preview screen thereby
switching to another preview screen... To provide a print set picture plane which can be easily used and understood by the user, in order to realize a technique for enabling a print setup in another... |
| US-6,615,345 |
System and method for regulating data capture in response to data strobe
using preamble, postamble and strobe... A computer system includes a memory bus, a memory device and a bridge. The memory device is adapted to furnish a data strobe signal to the memory bus and furnish... |
| US-6,615,344 |
System and method for tracking selectively enabling modules used in an
integrated processor using a tracking... An integrated processor is provided having functional unit tracking and monitoring capabilities. The processor core is configured to read configuration data and... |
| US-6,615,343 |
Mechanism for delivering precise exceptions in an out-of-order processor
with speculative execution A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set,... |
| US-6,615,342 |
Method and apparatus for object-oriented interrupt system An object-oriented interrupt processing system in a computer system creates a system database including a device namespace containing an entry for each device in... |
| US-6,615,341 |
Multiple-data bus architecture for a digital signal processor using
variable-length instruction set with single... A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations... |
| US-6,615,340 |
Extended operand management indicator structure and method Extended operand management indicators stored during initial program execution enable management and regulation of operand values and streamline their handling.... |
| US-6,615,339 |
VLIW processor accepting branching to any instruction in an instruction
word set to be executed consecutively A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation... |
| US-6,615,338 |
Clustered architecture in a VLIW processor A Very Long Instruction Word (VLIW) processor has a clustered architecture including a plurality of independent functional units and a multi-ported register file... |
| US-6,615,337 |
Method and apparatus for maintaining coherency in a translation lookaside
buffer In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer,... |
| US-6,615,336 |
Method for performing a medium access control address lookup in a network
switch of an ethernet network A method for performing a MAC address lookup in a network switch of an Ethernet network is provided, using a memory structure including a number of multi-slot... |
| US-6,615,335 |
Compressed storage of information Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into... |
| US-6,615,334 |
Method and apparatus for I/O data management with an I/O buffer in
compressed memory subsystem A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem.... |
| US-6,615,333 |
Data processing device, method of executing a program and method of
compiling A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A... |
| US-6,615,332 |
Storage system assuring data integrity and asynchronous remote data
duplexing A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a... |
| US-6,615,331 |
System and method to reduce cycle time by performing column redundancy
checks during a delay to accommodate... A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first... |
| US-6,615,330 |
Virtual worm method and system A system and method of storing data using write once read many (WORM) protection including using a hardware storage device to write data to a medium are... |
| US-6,615,329 |
Memory access control system, apparatus, and method Methods, circuitry, an apparatus, and a system for controlling access to a protected area of a memory are disclosed. The method includes detecting an attempt to... |
| US-6,615,328 |
Subsystem and method of reorganizing multiplexed data Disk units operable under control of different disk control units hold the same data. Under circumstances in which data is duplexed, when data is duplexed again... |
| US-6,615,327 |
Method and system for backing up data of data processing devices including
fixed length block format data... In a computer system that includes a first computer, a second computer, a first storage apparatus storing data in a fixed-length block format used by the second... |
| US-6,615,326 |
Methods and structure for sequencing of activation commands in a
high-performance DDR SDRAM memory controller Methods and structure in a memory controller for sequencing memory device page activation commands to improve memory bandwidth utilization. In a synchronous... |
| US-6,615,325 |
Method for switching between modes of operation An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used... |
| US-6,615,324 |
Embedded microprocessor multi-level security system in flash memory An embedded microprocessor two level security system in flash memory. The memory includes an address input and a memory space of addressable locations having a... |
| US-6,615,323 |
Optimizing pipelined snoop processing A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from... |
| US-6,615,322 |
Two-stage request protocol for accessing remote memory data in a NUMA data
processing system A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote... |
| US-6,615,321 |
Mechanism for collapsing store misses in an SMP computer system A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value... |
| US-6,615,320 |
Store collapsing mechanism for SMP computer system A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value... |
| US-6,615,319 |
Distributed mechanism for resolving cache coherence conflicts in a
multi-node computer architecture According to one embodiment, a method is disclosed. The method comprises receiving a read request from a first node in a multi-node computer system to read data... |
| US-6,615,318 |
Cache management system with multiple cache lists employing roving removal
and priority-based addition of cache... In a cache management system multiple cache lists are utilized, where each entry in a list names at least one corresponding data item in cache. A cache manager... |
| US-6,615,317 |
Methods and systems for providing a highly scalable synchronous data cache A data caching technique is provided that is highly scalable while being synchronous with an underlying persistent data source, such as a database management... |
| US-6,615,316 |
Using hardware counters to estimate cache warmth for process/thread
schedulers A method and computer system for estimating cache warmth for thread schedulers in a processor of a multiprocessor system. A mathematical model based upon a... |
| US-6,615,315 |
Fibre channel data storage system having improved fro-end I/O adapted hub A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a plurality of directors and... |
| US-6,615,314 |
Disk array and method for reading/writing data from/into disk unit When a bus is used as a data communication channel, data within a disk unit cannot be reproduced or copied into a spare disk while a control unit is making... |
| US-6,615,313 |
Disk input/output control device maintaining write data in multiple cache
memory modules and method and medium... An input/output control device uses all of its cache memory effectively and allows cache memory modules to be added in increments of one. When cache memory... |
| US-6,615,312 |
Method for processing file system service requests in a computer having an
attached disk drive that can... This invention is directed to a method for processing file system service requests in a computer having an attached disk drive that in response to commands from... |
| US-6,615,311 |
Method and system for updating a content addressable memory (CAM) that
prioritizes CAM entries according to... Updating a content addressable memory (CAM) involves identifying a new entry that is to be added to the CAM, identifying a free location in the CAM that is the... |
| US-6,615,310 |
Lossless data compressor with all CAM words available A method, system, and apparatus for making all content addressable memory words available for comparison in a data compressor is provided. In one embodiment, new... |
| US-6,615,309 |
Semiconductor memory device A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between... |
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