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| Patent # | Description |
|---|---|
| US-6,615,408 |
Method, system, and apparatus for providing action selections to an image
referencing a product in a video... Disclosed are a method, apparatus and system for providing action selections to an image referencing a product in a video production. According to the disclosure... |
| US-6,615,407 |
In-building CATV system, and up-converter and down-converter for use
therein A down-converter comprises a frequency division circuit, PLL, and local oscillation circuit to convert a signal from a reference oscillation circuit to a... |
| US-6,615,406 |
Apparatus for use in the manufacture of a computer system An apparatus for use in the manufacture of a computer system comprises a step table and a component table. The step table contains substantially all software... |
| US-6,615,405 |
Method and system for distributing and maintaining software across a
computer network A method and system are provided for installing software on microprocessor based devices accessible over a computer network. The method includes, identifying... |
| US-6,615,404 |
Method and apparatus for downloading software into an embedded-system Method for upgrading operating software and/or initialization program versions of an embedded system by using a single non-volatile memory. The non-volatile... |
| US-6,615,403 |
Compare speculation in software-pipelined loops The present invention provides a mechanism for implementing compare speculation in software pipelined loops. A data dependency graph (DDG) is generated for a... |
| US-6,615,402 |
Interchangeable FPGA-gate array A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an... |
| US-6,615,401 |
Blocked net buffer insertion A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time... |
| US-6,615,400 |
Optimizing dense via arrays of shrunk integrated circuit designs A method and apparatus for replacing dense via arrays in shrunk, electronic device designs involves identifying vias on the same node within the electronic... |
| US-6,615,399 |
Semiconductor device having dummy pattern A semiconductor device includes a real pattern and dummy patterns in respective different coordinate systems. Using a dummy pattern in a single coordinate system... |
| US-6,615,398 |
Method for dividing ROM and DDFS using the same method The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to... |
| US-6,615,397 |
Optimal clock timing schedule for an integrated circuit A netlist graph of an IC cell contains cell pin vertices, auxiliary vertices, and edges between vertices having a length. A clock shift SH(V) is assigned to each... |
| US-6,615,396 |
Searching for a path through a circuit Searching for a target path in a sequential circuit having plural paths includes (i) locating-a reference point on the circuit from which circuit timing... |
| US-6,615,395 |
Method for handling coupling effects in static timing analysis A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is... |
| US-6,615,394 |
Method and apparatus for preparing a simulation model for semiconductor
integrated circuit at power terminal... The present invention provides a method of forming a model for a circuit for simulating an electromagnetic interference, the model being described by a... |
| US-6,615,393 |
Method and apparatus for performing electrical distance check A method and apparatus for verification of a semiconductor device design is disclosed that includes the determination of electrical distance for shapes of a... |
| US-6,615,392 |
Hierarchical design and test method and system, program product embodying
the method and integrated circuit... A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and ... |
| US-6,615,391 |
Current controlled multi-state parallel test for semiconductor device A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and... |
| US-6,615,390 |
Method of manufacturing IC cards A IC card producing method includes testing steps which can enhance the reliability and generality of IC cards. The method of producing IC cards of the... |
| US-6,615,389 |
Database for designing integrated circuit device, and method for designing
integrated circuit device In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes:... |
| US-6,615,388 |
Low power path memory for viterbi decoders A path memory for a Viterbi decoder stores 2.sup.k-1 path select command signals generated a T interval earlier than reference clock timing. In response to a... |
| US-6,615,387 |
Method and apparatus for error detection An error correction and miscorrection detection apparatus includes a memory buffer for storing user data contained in a data signal. A syndrome computer circuit... |
| US-6,615,386 |
Error correcting apparatus Disclosed herein is an error correcting apparatus for receiving a signal subjected to a repetition processing in which a part of bits of an error-correction code... |
| US-6,615,385 |
Iterative decoder and an iterative decoding method for a communication
system An iterative decoder and iterative decoding method. In the iterative decoder, a first adder has a first port for receiving information symbols and a second port.... |
| US-6,615,384 |
Encoding/decoding method and apparatus and disk storage device An encoding/decoding apparatus generates data sequences with first and second interleave structures by respectively performing data on a data sequence to be... |
| US-6,615,383 |
System and method for message transmission between network nodes connected
by parallel links A first computer sends a sequence of messages to a second computer using remote write operations to directly store each message in a corresponding memory... |
| US-6,615,382 |
Method for controlling errors in link layer in wideband wireless
communication and computer readable media therefor A method for controlling errors in a wireless link layer using a simultaneous multiple copy scheme and an adaptive forward error correction (FEC) scheme in a... |
| US-6,615,381 |
Digital data transmitting/receiving method, base station unit used for
transmitting/receiving digital data, and... The present invention provides a digital data transmitting/receiving method, a base station unit, and a mobile object terminal unit, which enable collection of... |
| US-6,615,380 |
Dynamic scan chains and test pattern generation methodologies therefor According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. The scan... |
| US-6,615,379 |
Method and apparatus for testing a logic device Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some... |
| US-6,615,378 |
Method and apparatus for holding failing information of a memory built-in
self-test A network interface controller arrangement and a method of testing a memory arrangement uses a register to hold failing information from a memory built-in self... |
| US-6,615,377 |
Integrated circuit with signal-vector queue for normal and test modes of
operation An integrated circuit with enhanced testability provides a normal-operation mode of operation with an observability function matching that used in a test-drive... |
| US-6,615,376 |
Method and system for external notification and/or resolution of software
errors A method of providing external notification of an error includes detecting an error during an execution of a program command in a first set of commands in a... |
| US-6,615,375 |
Method and apparatus for tolerating unrecoverable errors in a
multi-processor data processing system A directory-based multi-processor computer system is provided with a mechanism for tolerating errors by providing the capability of checking data for errors and,... |
| US-6,615,374 |
First and next error identification for integrated circuit devices An integrated circuit device performs first and next error identification. An error condition associated with an integrated circuit device function is detected.... |
| US-6,615,373 |
Method, system and program products for resolving potential deadlocks A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to... |
| US-6,615,372 |
Method of retrieving and displaying problematic information about a printer
prior to a print job being printed... A method of printing a document, for example, on a recording medium of a printer selected by a user. Problematic information is retrieved about the printer in... |
| US-6,615,371 |
Trace reporting method and system A system and method for recording, storing, transferring and viewing trace data from a processor with an embedded trace macrocell. The system provides for... |
| US-6,615,370 |
Circuit for storing trace information A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a... |
| US-6,615,369 |
Logic analyzer with trigger specification defined by waveform exemplar Waveform segment(s) of interest in the displayed logic analyzer trace can create the desire in an operator to re-define the trigger specification to be those... |
| US-6,615,368 |
System and method for debugging highly integrated data processors There is disclosed a data processor having improved debugging features that output from the data processor selected instructions, data, or addresses in response... |
| US-6,615,367 |
Method and apparatus for diagnosing difficult to diagnose faults in a
complex system A method and apparatus for determining the root cause of no trouble found events in a machine is disclosed. The actual faults occurring during a predetermined... |
| US-6,615,366 |
Microprocessor with dual execution core operable in high reliability mode A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to... |
| US-6,615,365 |
Storing a computer disk image within an imaged partition The invention provides systems and methods for storing and recovering images in a computer partition, and more particularly to tools and techniques for placing... |
| US-6,615,364 |
Computer system and methods for acquiring dump information and system
recovery A dump information acquiring method and a system recovery method for a computer system using a virtual memory, the methods being used when fault occurs in the... |
| US-6,615,363 |
Optical disk and method of recording on the same An optical disk and method of recording information on the same are provided in which music and images such as, motion pictures can be recorded without dropout... |
| US-6,615,362 |
System and method for fault recovery for two line bi-directional ring
network The present invention provides a protection protocol for fault recovery, such as a ring wrap, for a network, such as a two line bi-directional ring network. An... |
| US-6,615,361 |
Obtaining a phase error of a clock signal A phase error of a clock signal is obtained by obtaining a data signal based on the clock signal, determining the phase error of the clock signal based on the... |
| US-6,615,360 |
Method and system for controlling a power on sequence in response to
monitoring respective components of a... A method of controlling the power-on of a computer system by providing a plurality of monitor lines interconnected with respective components of the computer... |
| US-6,615,359 |
Modified license key entry for pre-installation of software A method and computer system according to the disclosed invention allows the pre-installation of a software application without a license key. The computer... |
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