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| Patent # | Description |
|---|---|
| US-6,751,152 |
Method and configuration to allow a lower wordline boosted voltage
operation while increasing a sensing signal... A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of... |
| US-6,751,151 |
Ultra high-speed DDP-SRAM cache An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1)... |
| US-6,751,150 |
Circuits and method to protect a gate dielectric antifuse According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse,... |
| US-6,751,149 |
Magnetic tunneling junction antifuse device An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the... |
| US-6,751,148 |
Circuit for generating control signal using make-link type fuse A control signal generating circuit including a make-link type fuse is provided. The circuit includes a first transistor for receiving an input signal at a gate... |
| US-6,751,147 |
Method for adaptively writing a magnetic random access memory A method of adaptively writing magnetic memory cells of a MRAM is disclosed according to an embodiment of the present invention. The method comprises providing a... |
| US-6,751,146 |
System and method for charge restoration in a non-volatile memory device A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the... |
| US-6,751,145 |
Volatile semiconductor memory and mobile device The volatile semiconductor memory is constructed from a plurality of memory segments. The information stored in the memory cells must be regularly reconditioned.... |
| US-6,751,144 |
Semiconductor storage and method for testing the same A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power... |
| US-6,751,143 |
Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data... |
| US-6,751,142 |
Semiconductor memory device equipped with dummy cells There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The... |
| US-6,751,141 |
Differential charge transfer sense amplifier A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The... |
| US-6,751,140 |
Method for testing integrated semiconductor memory devices In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the... |
| US-6,751,139 |
Integrated circuit reset circuitry An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test... |
| US-6,751,138 |
Semiconductor integrated circuit device A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps... |
| US-6,751,137 |
Column repair circuit in ferroelectric memory A column repair circuit in a non-volatile ferroelectric memory having main columns and redundancy columns includes a data input/output buffer part for data... |
| US-6,751,136 |
Drive failure recovery via capacity reconfiguration A method, program and system for recovering data from a failed drive in a RAID system are provided. The invention comprises assigning a plurality of storage... |
| US-6,751,135 |
Method for driving memory cells of a dynamic semiconductor memory and
circuit configuration A dynamic semiconductor memory has memory cells disposed in a cell field. The memory cells are connected to master word lines by way of a word line driver for... |
| US-6,751,134 |
Internal voltage generating apparatus for a semiconductor memory device An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to... |
| US-6,751,133 |
Semiconductor memory which has reduced fluctuation of writing speed The non-volatile semiconductor memory of the present invention is comprised of: a memory cell array including a plurality of memory cells which is disposed at... |
| US-6,751,132 |
Semiconductor memory device and voltage generating method thereof A semiconductor memory device which provides an improved operation performance in response to a relatively low external power voltage is included. The device... |
| US-6,751,131 |
Semiconductor storage device and information apparatus A semiconductor storage device includes: a memory array including a plurality of memory cells; a reference array including a plurality of reference cells; a... |
| US-6,751,130 |
Integrated memory device, method of operating an integrated memory, and
memory system having a plurality of... An integrated memory has a selection circuit for setting a selectable latency--relative to a clock signal between a beginning of a read access and the provision... |
| US-6,751,129 |
Efficient read, write methods for multi-state memory Methods and apparatus for efficiently writing data to and reading data from multi-state memory cells. According to one aspect of the present invention, a memory... |
| US-6,751,128 |
Semiconductor memory device having shortened testing time The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device... |
| US-6,751,127 |
Systems and methods for refreshing non-volatile memory The present invention is related to methods and systems for refreshing non-volatile memories. A rewrite operation is performed followed by a refresh operation.... |
| US-6,751,126 |
Clamping circuit and nonvolatile memory device using the same The present invention relates to a clamping circuit and a nonvolatile memory device using the same. Each of switching means driven by a gate voltage of a... |
| US-6,751,125 |
Gate voltage reduction in a memory read A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in... |
| US-6,751,124 |
Bit line setup and discharge circuit for programming non-volatile memory A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a... |
| US-6,751,123 |
Storage device counting error correction A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor... |
| US-6,751,122 |
Nonvolatile semiconductor memory device The nonvolatile semiconductor memory device includes a memory cell array containing a plurality of nonvolatile memory cells and an initial setup data region in... |
| US-6,751,121 |
Flash memory array architecture A flash memory array architecture. In one embodiment, a flash memory device comprises a first and second bank. Each bank has a pair of quadrants of memory cells.... |
| US-6,751,120 |
Clock synchronized non-volatile memory device At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the... |
| US-6,751,119 |
Clock synchronized non-volatile memory device A nonvolatile memory apparatus which includes a plurality of terminals including clock, command and other terminals, a control circuit, and a plurality of... |
| US-6,751,118 |
Array architecture and operating methods for digital multilevel nonvolatile
memory integrated circuit system Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system.... |
| US-6,751,117 |
Single ended row select for a MRAM device A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to... |
| US-6,751,116 |
Semiconductor memory device A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair... |
| US-6,751,114 |
Method for programming a memory cell A method for reading and verifying the state of a memory cell during a write operation before writing allows a decision to be made whether to write to the cell... |
| US-6,751,113 |
Arrangement of integrated circuits in a memory module Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity... |
| US-6,751,112 |
Dense content addressable memory cell A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to... |
| US-6,751,111 |
High density memory cell A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being... |
| US-6,751,110 |
Static content addressable memory cell A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second... |
| US-6,751,109 |
Dual input AC/DC/ battery operated power supply A dual input battery assisted power converter (10) which provides a continuous, regulated DC voltage output to a user-connected mobile device, such as, a lap top... |
| US-6,751,108 |
Power supply input switching circuit improved with regard to line faults A power supply circuit and a switched-mode power supply with a power supply input circuit are proposed. Known power supply circuits comprise a rectifier supplied... |
| US-6,751,107 |
DC power supply device with constant power output level A DC power supply device includes transformers that operate with an enhanced efficiency and can reduce the factors that generate ripples in the output voltage to... |
| US-6,751,106 |
Cross current control for power converter systems and integrated magnetic
choke assembly A cross current control system for multiple, parallel-coupled power converters includes common mode chokes, local cross current feedback controllers, and local... |
| US-6,751,105 |
Method for controlling pwm pulse For an interval in which an Op-vector and a b-vector are successively output among intervals of output voltage vectors of each phase within a PWM cycle, the... |
| US-6,751,104 |
Single-stage power factor correction method to reduce energy storage
capacitor voltage and circuit for same A DC-to-DC converter is coupled to an AC source comprising a rectifier bridge. An input inductor is coupled to the output of the rectifier stage. An auxiliary... |
| US-6,751,103 |
Retainer clip A retainer clip for holding a battery to an electronic device is disclosed. The retainer clip includes at least three arms that join together at an intersecting... |
| US-6,751,102 |
Circuit board mounting apparatus A mounting apparatus includes a plurality of standoffs (1) bent from a bottom plate (10) a computer enclosure (5). Each standoff includes a support body (12)... |
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