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| Patent # | Description |
|---|---|
| US-6,751,753 |
Method, system, and program for monitoring system components Provided is a method, system, program, and data structure for deriving state information concerning a monitored system component. A status object is provided... |
| US-6,751,752 |
Checking events generated by a device A method of checking includes establishing links between events based on a set of event relationships, in an earlier pass through a time-ordered sequence of... |
| US-6,751,751 |
Universal multi-bus breakpoint unit for a configurable system-on-chip The present invention provides a hardware breakpoint unit for a multibus, processor-based, configurable circuit. The multi-bus breakpoint unit connects to and... |
| US-6,751,750 |
Method to protect and recover a write ahead log from interruptions The present invention is directed to a method of recovering a write ahead log after an interruption. In a first aspect of the present invention, a method of... |
| US-6,751,749 |
Method and apparatus for computer system reliability According to one embodiment, a multiprocessing system includes a first processor, a second processor, and compare logic. The first processor is operable to... |
| US-6,751,748 |
Context redundancy system on a wireless and packet-based telecommunications
network interface The present invention is a redundancy system in the interface between a wireless and packet-based telecommunications network. The redundancy system includes... |
| US-6,751,747 |
System, device, and method for detecting and recovering from failures in a
multicast communication system A system, device, and method for detecting and recovering from failures in a multicast communication system involves joining a multicast group over a primary... |
| US-6,751,746 |
Method and apparatus for uninterrupted packet transfer using replication
over disjoint paths A method of operating a fault tolerant connection in a network is described. The network includes a number of network elements and a number of links. Each of the... |
| US-6,751,745 |
Digital synchronization circuit provided with circuit for generating
polyphase clock signal A digital synchronization circuit 1000 according to the present invention includes: a polyphase clock generation circuit outputting a plurality of clock signals... |
| US-6,751,744 |
Method of integrated circuit design checking using progressive individual
network analysis A method for checking integrated circuit designs comprising the steps of calculating a first performance parameter by analyzing the network's sensitivity to a... |
| US-6,751,743 |
Method and apparatus for selecting a first clock and second clock for first
and second devices respectively... A method and apparatus for synchronizing clocks is provided that is flexible and compensates for process, voltage, and temperature (PVT) variations and other... |
| US-6,751,742 |
System for responding to a power saving mode and method thereof In one embodiment of the present invention, an application responds to a low power operation request based upon its current state. In another mode, the... |
| US-6,751,741 |
Computer power management apparatus and method for optimizing CPU
throttling A method to reduce the power dissipation of a system by omitting an unnecessary CPU throttling operation in a power management apparatus that performs the CPU... |
| US-6,751,740 |
Method and system for using a combined power detect and presence detect
signal to determine if a memory module... A system and method for providing a common power detect and presence detect signal. In one embodiment, a memory module includes a voltage regulator and a power... |
| US-6,751,739 |
System and method for adjusting a memory pool configuration by assessing
task performance of a specified... A method and related computer system that allow recalling at least one memory pooling profile, in response to user input, and pooling data processing system... |
| US-6,751,738 |
Firewall providing enhanced network security and user transparency The present invention, generally speaking, provides a firewall that achieves maximum network security and maximum user convenience. The firewall employs "envoys"... |
| US-6,751,737 |
Multiple protected mode execution environments using multiple register sets
and meta-protected instructions A system is provided that contains multiple control register and descriptor table register sets so that an execution context switch between X86 protected mode... |
| US-6,751,736 |
Method and apparatus for E-commerce by using optional fields for virtual
bar codes E-commerce web page forms contain an encrypted and encoded string, which contains basic information about a product for sale on the web page. Optional product... |
| US-6,751,735 |
Apparatus for control of cryptography implementations in third party
applications An apparatus and method provide a controlled, dynamically loaded, modular, cryptographic implementation for integration of flexible policy implementations on... |
| US-6,751,734 |
Authentication executing device, portable authentication device, and
authentication method using biometrics... An authentication method using biometrics identification, comprising the following steps of: identifying a user by biometrics entered from a portable... |
| US-6,751,733 |
Remote authentication system To obtain a remote authentication system that securely authenticates with protecting biometrics information, which is user's personal information, and is firm on... |
| US-6,751,732 |
Method and system for secure delivery and printing of documents via a
network device A system and method for providing secure, on-demand printing of documents delivered to a networked printing device is disclosed. A user logs onto a networked... |
| US-6,751,731 |
Piggy-backed key exchange protocol for providing secure, low-overhead
browser connections to a server with... A method, system, and computer program product for establishing security parameters that are used to exchange data on a secure connection. A piggy-backed key... |
| US-6,751,730 |
Method and apparatus for documenting cap removal data A method and apparatus is disclosed that documents and authenticates cap removal data. According to a first aspect of the present invention, the apparatus... |
| US-6,751,729 |
Automated operation and security system for virtual private networks A node device for providing secure communication services over a data network, such as the Internet or another public or private packet switched network, to... |
| US-6,751,728 |
System and method of transmitting encrypted packets through a network
access point A method and system for network communication efficiently transmits encrypted packets from a sending host on an external network to a receiving host on an... |
| US-6,751,727 |
Network communication device identification in a communication network An identification system is disclosed that is configured to identify communication devices on a network. The identification system is comprised of boot circuitry... |
| US-6,751,726 |
Method and system for loading fonts by caching font-loading information A method and system for efficiently loading fonts at the boot time of a computer uses a cache file to store font-loading information for the installed fonts. The... |
| US-6,751,725 |
Methods and apparatuses to clear state for operation of a stack Methods and apparatuses to clear state for operation of a stack. According to one embodiment of the invention, a processor comprises a set of one or more storage... |
| US-6,751,724 |
Method and apparatus for instruction fetching Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute ... |
| US-6,751,723 |
Field programmable gate array and microcontroller system-on-a-chip An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing... |
| US-6,751,722 |
Local control of multiple context processing elements with configuration
contexts A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores... |
| US-6,751,721 |
Broadcast invalidate scheme A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality... |
| US-6,751,720 |
Method and system for detecting and resolving virtual address synonyms in a
two-level cache hierarchy L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state ("Dtags") are... |
| US-6,751,719 |
Method and an apparatus to dynamically order features and to resolve
conflicts in a multiple-layer logical... A method and apparatus to dynamically order features and resolve conflicts in a logical volume management environment is provided. The method and apparatus... |
| US-6,751,718 |
Method, system and computer program product for using an instantaneous
memory deficit metric to detect and... A method, system and computer program product for detecting when insufficient RAM is available in a computer system, and estimating the additional RAM needed to... |
| US-6,751,717 |
Method and apparatus for clock synchronization between a system clock and a
burst data clock The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst... |
| US-6,751,716 |
Semiconductor storage device, control device, and electronic apparatus A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a... |
| US-6,751,715 |
System and method for disabling and recreating a snapshot volume The present invention is directed to a system and method for disabling and recreating a snapshot volume. A method of disabling repository volume activity... |
| US-6,751,714 |
Systems and methods for relocation of compressed data tracks Systems and methods are provided to backup, restore and relocate compressed data images, e.g., DASD compressed tracks, associated with virtual storage volumes. A... |
| US-6,751,713 |
Method and system for scheduled activation of system information tables in
digital transport streams A method and system for decoding a transport stream are disclosed. In one embodiment, the method includes receiving a system information table in the transport... |
| US-6,751,712 |
Circuit and method for executing access control of virtual channel memory
preventing deterioration of data... A VCSDRAM (Virtual Channel SDRAM) control circuit comprises an access request reception section, an access request storage section, a status comparison section,... |
| US-6,751,711 |
Methods and systems for process rollback in a shared memory parallel
processor computing environment Methods and systems for process rollback in a shared memory parallel processor computing environment use priority values to control process rollback. Process... |
| US-6,751,710 |
Scalable multiprocessor system and cache coherence method The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using... |
| US-6,751,709 |
Method and apparatus for prefetching objects into an object cache One embodiment of the present invention provides a system that uses references within a first object to prefetch a second object into a cache memory. During... |
| US-6,751,708 |
Method for ensuring that a line is present in an instruction cache A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch... |
| US-6,751,707 |
Methods and apparatus for controlling a cache memory Methods and apparatus for controlling a cache memory are described in which the overwriting of floating point data into any cache line of the cache memory is... |
| US-6,751,706 |
Multiple microprocessors with a shared cache A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having... |
| US-6,751,705 |
Cache line converter A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to... |
| US-6,751,704 |
Dual-L2 processor subsystem architecture for networking system A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2... |
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