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| Patent # | Description |
|---|---|
| US-6,751,803 |
Signal distribution circuit Received digital CATV signals are branched by a directional coupler into signals flowing in a through direction and signals flowing in a branch direction. The... |
| US-6,751,802 |
Method of transmitting and receiving compressed television signals The invention relates to the transmission of MPEG encoded television signals from a Video-On-Demand server (1) to a receiver (2) via a network (3). Non-linear... |
| US-6,751,801 |
Aircraft in-flight entertainment system having enhanced antenna steering
and associated methods An aircraft in-flight entertainment system includes a satellite TV receiver, at least one video display connected to the receiver, and a multi-beam antenna on... |
| US-6,751,800 |
Information processing apparatus, method, and computer-readable medium A system and method for creating multimedia information synchronized with a video signal (e.g., a program of a television broadcast) are provided. The multimedia... |
| US-6,751,799 |
In situ processing of remote procedure calls A computer network includes a client and a server which are preferably independently operable computers that cooperate to perform different procedures of an... |
| US-6,751,798 |
Method and apparatus for performing distributed object calls using proxies
and memory allocation A method and apparatus for performing distributed object calls uses proxies and memory allocation and deallocation. Specifically, an object reference to an... |
| US-6,751,797 |
System and method for managing the persistence of EJB components in a
directory accessed via LDAP The present invention relates to a method for managing the persistence of EJB components (8) integrated into an EJB server (3) of a computer system (1),... |
| US-6,751,796 |
Integration of systems management services with an underlying system object
model A systems management subsystem provides resources for managing components and allows components to be manageable. In particular, state information about managed... |
| US-6,751,795 |
System and method for software installation The system for software installation of the present invention comprises: a storage medium for storing a file to be installed; a difference detector for comparing... |
| US-6,751,794 |
Intelligent patch checker A method to remotely update software for a plurality of client system is disclosed. A client system sends a request for an upgrade to a server system. The... |
| US-6,751,793 |
System and method for growing a hierarchical structure with new virtual
base classes while preserving... In accordance with the method of invention, a class hierarchy is derived which maintains release-to-release binary compatibility. Leftmost classes of the class... |
| US-6,751,792 |
Using value-expression graphs for data-flow optimizations A new method and apparatus for use in post compilation optimizers is presented. The present invention is based on the use of a new graphical representation of... |
| US-6,751,791 |
Method of optimizing an MPI procedure by altering to a procedure other than
the invoked MPI procedure portion... A method is disclosed for optimizing an MPI procedure by altering to a procedure other than the MPI procedure invocation portion or by altering the execution... |
| US-6,751,790 |
Frameworks for efficient representation of string objects in Java
programming environments Alternative techniques for representation of Java string objects are needed. The techniques are especially useful for representing Java objects in Java computing... |
| US-6,751,789 |
Method and system for periodic trace sampling for real-time generation of
segments of call stack trees... A method and system for profiling a program using periodic trace sampling is provided. During the execution of the program, sample-based profiling of the... |
| US-6,751,788 |
Method of testing computer software A method of testing the ability of software modules, each executing particular functions, in a device to cooperate using machine code sequences contained in... |
| US-6,751,787 |
Graphical programming language for representations of concurrent operations A simplified programming language is disclosed. The main flow of the program is enclosed in one or more frames. Concurrent operations and asynchronous events... |
| US-6,751,786 |
Clock tree synthesis for a hierarchically partitioned IC layout A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top... |
| US-6,751,785 |
System and method for limiting increase in capacitance due to dummy metal
fills utilized for improving planar... Systems and methods for limiting capacitance increase due to dummy fill metals utilized to improve planar profile uniformity are disclosed. A computer-automated... |
| US-6,751,784 |
Implementation of networks using parallel and series elements The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of... |
| US-6,751,783 |
System and method for optimizing an integrated circuit design The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC,... |
| US-6,751,782 |
Method and apparatus for analog compensation of driver output signal slew
rate against device impedance variation A method and apparatus for analog compensation of driver output signal slew rate against device impedance variation is described. The method includes a signal... |
| US-6,751,781 |
Thermal data automatic service system An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a... |
| US-6,751,780 |
User interface for initiating the export of an optimized scanned document
using drag and drop A user interface method for launching an optimized final scan of a selected region of interest selected from a preview scan of a document. A user may drag the... |
| US-6,751,779 |
Apparatus and method for processing document image In a document image processing apparatus, a document image is inputted as image data from an image inputting section. In a layout analyzing section, the layout... |
| US-6,751,778 |
Information server systems and methods of rendering information pages Methods and systems for rendering information pages are described. A page is divided into panes which are rendered by individual pane renderers. The pane... |
| US-6,751,777 |
Multi-target links for navigating between hypertext documents and the like An apparatus, program product, and method utilize a multi-target link to selectively access data located at one or more of a plurality of storage locations... |
| US-6,751,776 |
Method and apparatus for personalized multimedia summarization based upon
user specified theme An automatic video content summarization system that is able to create personalized multimedia summary based on the user-specified theme. The invention employs... |
| US-6,751,775 |
Tap-selectable reduced state sequence estimator A method of determining a trellis from a sequence of n symbols in a Viterbi detector. The method includes the steps of receiving a sequence of n symbols,... |
| US-6,751,774 |
Rate (M/N) code encoder, detector, and decoder for control data A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater... |
| US-6,751,773 |
Coding apparatus capable of high speed operation A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and... |
| US-6,751,772 |
Rate matching device and method for a data communication system A device and method for rate matching channel-encoded symbols in a data communication system. The rate matching device and method can be applied to a data... |
| US-6,751,771 |
Method and apparatus for error processing in optical disk memories The present invention more efficiently retrieves and processes data stored on an optical disk in a DVD-ROM format. Generally, the retrieval and processing of... |
| US-6,751,770 |
Decoder for iterative decoding of binary cyclic codes A decoder for performing soft decision iterative decoding of a cyclic code based on belief propagation, includes an information exchange control unit, an X... |
| US-6,751,769 |
(146,130) error correction code utilizing address information A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array... |
| US-6,751,768 |
Hierarchical creation of vectors for quiescent current (IDDQ) tests for
system-on-chip circuits A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions... |
| US-6,751,767 |
Test pattern compression method, apparatus, system and storage medium A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to... |
| US-6,751,766 |
Increasing the effectiveness of error correction codes and operating
multi-level memory systems by using... The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data... |
| US-6,751,765 |
Method and system for determining repeatable yield detractors of integrated
circuits An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns... |
| US-6,751,764 |
Method and apparatus for testing and debugging a circuit A series of secondary or "shadow" storage elements are employed that duplicate, or "shadow", the information in a circuit's core logic shadowed functional... |
| US-6,751,763 |
Semiconductor device test method for optimizing test time A method of testing a semiconductor device begins by reading test information into a testing apparatus. The test information is used to determine whether to... |
| US-6,751,762 |
Systems and methods for testing a memory Systems and methods for testing a memory array in an integrated circuit. The method provides a favorable tradeoff between test time and quality of test results,... |
| US-6,751,761 |
Method and apparatus for testing network, and recording medium The present invention relates to a node connection test method and a recording medium by which a test can be carried out in a system having a plurality of nodes... |
| US-6,751,760 |
Method and system for performing memory repair analysis A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing... |
| US-6,751,759 |
Method and apparatus for pipeline hazard detection A method and apparatus for identifying and detecting hazards is presented. An executable specification for the architecture is compiled that includes ... |
| US-6,751,758 |
Method and system for handling errors in a data storage environment The present invention is a system and method for providing clarity and simplicity to the task of screening for errors occurring in a data storage system and... |
| US-6,751,757 |
Disk drive data protection using clusters containing error detection
sectors The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive.... |
| US-6,751,756 |
First level cache parity error inject A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to... |
| US-6,751,755 |
Content addressable memory having redundancy capabilities According to one embodiment, a content addressable memory (CAM) (100) can include a number of ordinary rows (102-0 to 102-n) that provide ordinary match... |
| US-6,751,754 |
Single step debug card using the PCI interface This specification discloses a single step debug card using the PCI bus, which keeps the FRAME# of the PCI bus at a low voltage; latches and displays through an... |
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