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| Patent # | Description |
|---|---|
| US-6,798,728 |
Optical disk device and luminescent power control method for semiconductor
laser A means for measuring the temperature in the surroundings of a semiconductor laser is provided and, if the temperature is not above a certain level, power... |
| US-6,798,727 |
Optical pickup apparatus A reflective mirror 14 is inclined and placed with respect to an objective lens 16 and a photoelectric conversion element 15 for monitor is placed in the back... |
| US-6,798,726 |
Data decoding An optical disk data decoder generates estimates of serial input signal values by slicing them into samples. The data sequences contained in each sample are... |
| US-6,798,725 |
Wave-shaping apparatus and reproduction signal processing apparatus
including the same A wave-shaping apparatus includes a first detection circuit for detecting a reproduction signal reproduced from an optical disk by an optical pickup circuit... |
| US-6,798,724 |
Low cost detection of wobble inversions using a tuned circuit A tuned circuit is used to detect wobble clock inversions. The tuned circuit reacts to a wobble inversion with a change in amplitude that may be detected by a... |
| US-6,798,723 |
Optical pickup head and information recording/reproducing device An optical pickup head is provided with a light source, a diffracting means for creating a plurality of diffracted beams, a converging means for focusing the... |
| US-6,798,722 |
Hand and timepiece using the hand To provide a hand, free from hand deviation and disengagement, having integrated engaging and wing portions and formed of a low-density material. A hand body has... |
| US-6,798,721 |
Electronic timepiece An electronic timepiece adapted to minimize a horizontal slippage of contact terminals when a display unit housing is diagonally fitted in a case. A liquid... |
| US-6,798,720 |
Projection alarm clock The invention relates to a novel design for a projection alarm clock for displaying various values by means of projection, using a projector with one optical... |
| US-6,798,719 |
Electronic device including warranty start date An electronic device has a central processing unit (CPU), a display, and a memory device. The display and memory device are both coupled to the CPU. The memory... |
| US-6,798,718 |
Sensor timepiece, sensor timepiece data input system and method, and
computer readable recording medium To make calibration of temperature compensation etc. of individual sensor timepieces straightforward, to carry out measurements of physical quantities by each... |
| US-6,798,717 |
High density pixel array A pixel array device is fabricated by a laser micro-milling method under strict process control conditions. The device has an array of pixels bonded together... |
| US-6,798,716 |
System and method for wireless electrical power transmission A power transmission system using directional ultrasound for power transmission includes a transmitting device and a receiving device. The transmitting device... |
| US-6,798,715 |
Biomimetic sonar system and method The Biomimetic Sonar invention ensonifies submerged objects, digitizes acoustic images reflected from the ensonified objects, and classifies and stores the... |
| US-6,798,714 |
Method of performing stretch-free normal moveout (NMO) and stacking of
seismic traces A method of performing normal moveout (NMO) correction and stacking of a common-midpoint (CMP) gather of seismic traces in a manner that avoids NMO stretch is... |
| US-6,798,713 |
Implementing software breakpoints Program code for a Processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile... |
| US-6,798,712 |
Wordline latching in semiconductor memories A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the... |
| US-6,798,711 |
Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on... |
| US-6,798,710 |
Synchronous flash memory with virtual segment architecture An improved memory device and architecture has been detailed that enhances a Flash memory device that has an SDRAM compatible interface. The memory device... |
| US-6,798,709 |
Memory device having dual power ports and memory system including the same A plurality of internal circuits of a memory device are operable at first and second internal voltages, where the first internal voltage is less than the second... |
| US-6,798,708 |
Memory controller and serial memory In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal... |
| US-6,798,707 |
Memory control apparatus for serial memory A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an... |
| US-6,798,706 |
Integrated circuit with temperature sensor and method for heating the
circuit A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least... |
| US-6,798,705 |
Noise resistant small signal sensing circuit for a memory device Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus... |
| US-6,798,704 |
High Speed sense amplifier data-hold circuit for single-ended SRAM A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays... |
| US-6,798,703 |
Semiconductor memory device having improved replacement efficiency of
defective word lines by redundancy word lines A semiconductor memory device that efficiently replaces defective word lines by redundancy word lines. The semiconductor memory device includes a plurality of... |
| US-6,798,702 |
Semiconductor memory device capable of testing data line redundancy
replacement circuit In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N2 corresponding to ith write data line to node N4 corresponding... |
| US-6,798,701 |
Semiconductor integrated circuit device having data input/output
configuration variable In an embedded DRAM core of which word configuration can be varied, a modifying circuit selects either word configuration designating information from a metal... |
| US-6,798,700 |
Methods of reading and/or writing data to memory devices including multiple
write circuits and/or virtual... Methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory... |
| US-6,798,699 |
Flash memory device and method of erasing A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming,... |
| US-6,798,698 |
Nonvolatile semiconductor memory device A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program... |
| US-6,798,697 |
Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address... |
| US-6,798,696 |
Method of controlling the operation of non-volatile semiconductor memory
chips Disclosed herewith is a method for controlling the operation of non-volatile semiconductor chips with high sequential access performance realized by smoothing... |
| US-6,798,695 |
Arrangement for storing a count In an arrangement for storing a count, which comprises a non-volatile memory (1) which has at least 3 memory segments (2, 3, 4), a controller (5) is provided... |
| US-6,798,694 |
Method for reducing drain disturb in programming For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while... |
| US-6,798,693 |
Semiconductor memory cell and memory array using a breakdown phenomena in
an ultra-thin dielectric A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by... |
| US-6,798,692 |
Programmable sub-surface aggregating metallization structure and method of
making same A programmable sub-surface aggregating metallization structure ("PSAM") includes an ion conductor such as a chalcogenide-glass which includes metal ions and at... |
| US-6,798,691 |
Asymmetric dot shape for increasing select-unselect margin in MRAM devices A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory... |
| US-6,798,690 |
Magnetic switching with expanded hard-axis magnetization volume at
magnetoresistive bit ends A magnetoresistive apparatus and method of operation with improved switching characteristics is provided. Switching of a magnetic direction of a magnetic layer... |
| US-6,798,689 |
Integrated memory with a configuration of non-volatile memory cells and
method for fabricating and for... An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive... |
| US-6,798,688 |
Storage array such as a SRAM with reduced power requirements A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI)... |
| US-6,798,687 |
System and method for effectively implementing a high speed DRAM device A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a... |
| US-6,798,686 |
Semiconductor device In a semiconductor memory device comprising a cell array of memory cells each including a cell transistor and a capacitor, word lines and bit line pairs, the... |
| US-6,798,685 |
Multi-output multiplexor Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to... |
| US-6,798,684 |
Methods and systems for programmable memory using silicided poly-silicon
fuses The present invention is directed to methods and systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive... |
| US-6,798,683 |
Pattern layout of transfer transistors employed in row decoder A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows... |
| US-6,798,682 |
Reduced integrated circuit chip leakage and method of reducing leakage An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other... |
| US-6,798,681 |
DRAM A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an... |
| US-6,798,680 |
Read-only MOS memory A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection... |
| US-6,798,679 |
Semiconductor memory module A bare chip is provided with a pad for activation/deactivation control to which a deactivation control signal for converting a bare chip that has been detected... |
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